Home
last modified time | relevance | path

Searched refs:CLK (Results 1 – 25 of 46) sorted by relevance

12

/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c17 #define CLK 0 macro
131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
144 regmap_write(regmap, 0x32, val[CLK]); in dphy_set_timing_reg()
150 regmap_write(regmap, 0x91, val[CLK]); in dphy_set_timing_reg()
157 regmap_write(regmap, 0x33, val[CLK]); in dphy_set_timing_reg()
163 regmap_write(regmap, 0x92, val[CLK]); in dphy_set_timing_reg()
170 regmap_write(regmap, 0x34, val[CLK]); in dphy_set_timing_reg()
176 regmap_write(regmap, 0x93, val[CLK]); in dphy_set_timing_reg()
183 regmap_write(regmap, 0x36, val[CLK]); in dphy_set_timing_reg()
[all …]
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap5-dss.txt77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
99 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,omap4-dss.txt96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
118 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,dra7-dss.txt73 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,omap3-dss.txt86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dddc_regs.h158 DDC_REG_LIST(CLK, id)\
168 DDC_VGA_REG_LIST(CLK)\
187 DDC_REG_LIST_DCN2(CLK, id)\
/linux/arch/arm/boot/dts/st/
H A Dstm32f7-pinctrl.dtsi241 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
254 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
272 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
283 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
296 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
314 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
H A Dste-href-family-pinctrl.dtsi29 "GPIO217_AH12"; /* CLK */
49 pins = "GPIO217_AH12"; /* CLK */
66 pins = "GPIO217_AH12"; /* CLK */
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u11-smarc-du-adv7513.dtso59 pinmux = <RZG2L_PORT_PINMUX(11, 3, 6)>; /* CLK */
H A Dr8a779g3-sparrow-hawk.dts145 /* Page 26 / PCIe.0/1 CLK */
327 line-name = "PCIe-CLK-nOE-M2";
335 line-name = "PCIe-CLK-nOE-USB";
462 /* Page 26 / PCIe.0/1 CLK */
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-h2-plus-bananapi-m2-zero.dts234 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
241 "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
H A Dsun7i-a20-bananapi.dts256 "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3",
273 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
H A Dsun6i-a31s-sinovoip-bpi-m2.dts281 "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK",
302 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
/linux/drivers/pinctrl/
H A Dpinctrl-th1520.c182 TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0),
185 TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0),
265 TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0),
266 TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0),
267 TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0),
268 TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0),
/linux/arch/arm64/boot/dts/freescale/
H A Dimx95-phycore-fpsc.dtsi564 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e /* CLK */
578 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e /* CLK */
591 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe /* CLK */
/linux/arch/arm/mach-omap1/
H A Dclock.h25 #define CLK(dev, con, ck, cp) \ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c139 DDC_GPIO_VGA_REG_LIST(CLK),
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c135 DDC_GPIO_VGA_REG_LIST(CLK),
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c129 DDC_GPIO_VGA_REG_LIST(CLK),
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c128 DDC_GPIO_VGA_REG_LIST(CLK),
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_factory_dcn401.c131 DDC_GPIO_VGA_REG_LIST(CLK),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-rfb1.dts277 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
421 * DAT2, DAT3, CMD, CLK for SD respectively.
H A Dmt7622-bananapi-bpi-r64.dts338 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
487 * DAT2, DAT3, CMD, CLK for SD respectively.
/linux/Documentation/devicetree/bindings/regulator/
H A Dtps6586x.txt85 regulator-name = "PCIE CLK";
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-clearfog-gt-8k.dts432 * [9.11]CP1 SPI0 MOSI/MISO/CLK
436 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)

12