1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2013 Linaro Ltd. 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include "ste-dbx5x0-pinctrl.dtsi" 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring soc { 10*724ba675SRob Herring pinctrl { 11*724ba675SRob Herring /* Settings for all SPI default and sleep states */ 12*724ba675SRob Herring spi2 { 13*724ba675SRob Herring spi2_default_mode: spi_default { 14*724ba675SRob Herring default_mux { 15*724ba675SRob Herring function = "spi2"; 16*724ba675SRob Herring groups = "spi2_oc1_2"; 17*724ba675SRob Herring }; 18*724ba675SRob Herring default_cfg1 { 19*724ba675SRob Herring pins = "GPIO216_AG12"; /* FRM */ 20*724ba675SRob Herring ste,config = <&gpio_out_hi>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring default_cfg2 { 23*724ba675SRob Herring pins = "GPIO218_AH11"; /* RXD */ 24*724ba675SRob Herring ste,config = <&in_pd>; 25*724ba675SRob Herring }; 26*724ba675SRob Herring default_cfg3 { 27*724ba675SRob Herring pins = 28*724ba675SRob Herring "GPIO215_AH13", /* TXD */ 29*724ba675SRob Herring "GPIO217_AH12"; /* CLK */ 30*724ba675SRob Herring ste,config = <&out_lo>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring }; 33*724ba675SRob Herring 34*724ba675SRob Herring spi2_idle_mode: spi_idle { 35*724ba675SRob Herring /* 36*724ba675SRob Herring * The idle mode is basically sleep mode sans wakeups. Also 37*724ba675SRob Herring * note that we have muxes the pins off the function here 38*724ba675SRob Herring * as we do not state any muxing. 39*724ba675SRob Herring */ 40*724ba675SRob Herring idle_cfg1 { 41*724ba675SRob Herring pins = "GPIO218_AH11"; /* RXD */ 42*724ba675SRob Herring ste,config = <&slpm_in_pdis>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring idle_cfg2 { 45*724ba675SRob Herring pins = "GPIO215_AH13"; /* TXD */ 46*724ba675SRob Herring ste,config = <&slpm_out_lo_pdis>; 47*724ba675SRob Herring }; 48*724ba675SRob Herring idle_cfg3 { 49*724ba675SRob Herring pins = "GPIO217_AH12"; /* CLK */ 50*724ba675SRob Herring ste,config = <&slpm_pdis>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring spi2_sleep_mode: spi_sleep { 55*724ba675SRob Herring sleep_cfg1 { 56*724ba675SRob Herring pins = 57*724ba675SRob Herring "GPIO216_AG12", /* FRM */ 58*724ba675SRob Herring "GPIO218_AH11"; /* RXD */ 59*724ba675SRob Herring ste,config = <&slpm_in_wkup_pdis>; 60*724ba675SRob Herring }; 61*724ba675SRob Herring sleep_cfg2 { 62*724ba675SRob Herring pins = "GPIO215_AH13"; /* TXD */ 63*724ba675SRob Herring ste,config = <&slpm_out_lo_wkup_pdis>; 64*724ba675SRob Herring }; 65*724ba675SRob Herring sleep_cfg3 { 66*724ba675SRob Herring pins = "GPIO217_AH12"; /* CLK */ 67*724ba675SRob Herring ste,config = <&slpm_wkup_pdis>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring }; 71*724ba675SRob Herring 72*724ba675SRob Herring mcde { 73*724ba675SRob Herring lcd_default_mode: lcd_default { 74*724ba675SRob Herring default_mux1 { 75*724ba675SRob Herring /* Mux in VSI0 and all the data lines */ 76*724ba675SRob Herring function = "lcd"; 77*724ba675SRob Herring groups = 78*724ba675SRob Herring "lcdvsi0_a_1", /* VSI0 for LCD */ 79*724ba675SRob Herring "lcd_d0_d7_a_1", /* Data lines */ 80*724ba675SRob Herring "lcdvsi1_a_1"; /* VSI1 for HDMI */ 81*724ba675SRob Herring }; 82*724ba675SRob Herring default_mux2 { 83*724ba675SRob Herring function = "lcda"; 84*724ba675SRob Herring groups = 85*724ba675SRob Herring "lcdaclk_b_1"; /* Clock line for TV-out */ 86*724ba675SRob Herring }; 87*724ba675SRob Herring default_cfg1 { 88*724ba675SRob Herring pins = 89*724ba675SRob Herring "GPIO68_E1", /* VSI0 */ 90*724ba675SRob Herring "GPIO69_E2"; /* VSI1 */ 91*724ba675SRob Herring ste,config = <&in_pu>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring }; 94*724ba675SRob Herring lcd_sleep_mode: lcd_sleep { 95*724ba675SRob Herring sleep_cfg1 { 96*724ba675SRob Herring pins = "GPIO69_E2"; /* VSI1 */ 97*724ba675SRob Herring ste,config = <&slpm_in_wkup_pdis>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring }; 100*724ba675SRob Herring }; 101*724ba675SRob Herring 102*724ba675SRob Herring ske { 103*724ba675SRob Herring /* SKE keys on position 2 in an 8x8 matrix */ 104*724ba675SRob Herring ske_kpa2_default_mode: ske_kpa2_default { 105*724ba675SRob Herring default_mux { 106*724ba675SRob Herring function = "kp"; 107*724ba675SRob Herring groups = "kp_a_2"; 108*724ba675SRob Herring }; 109*724ba675SRob Herring default_cfg1 { 110*724ba675SRob Herring pins = 111*724ba675SRob Herring "GPIO153_B17", /* I7 */ 112*724ba675SRob Herring "GPIO154_C16", /* I6 */ 113*724ba675SRob Herring "GPIO155_C19", /* I5 */ 114*724ba675SRob Herring "GPIO156_C17", /* I4 */ 115*724ba675SRob Herring "GPIO161_D21", /* I3 */ 116*724ba675SRob Herring "GPIO162_D20", /* I2 */ 117*724ba675SRob Herring "GPIO163_C20", /* I1 */ 118*724ba675SRob Herring "GPIO164_B21"; /* I0 */ 119*724ba675SRob Herring ste,config = <&in_pd>; 120*724ba675SRob Herring }; 121*724ba675SRob Herring default_cfg2 { 122*724ba675SRob Herring pins = 123*724ba675SRob Herring "GPIO157_A18", /* O7 */ 124*724ba675SRob Herring "GPIO158_C18", /* O6 */ 125*724ba675SRob Herring "GPIO159_B19", /* O5 */ 126*724ba675SRob Herring "GPIO160_B20", /* O4 */ 127*724ba675SRob Herring "GPIO165_C21", /* O3 */ 128*724ba675SRob Herring "GPIO166_A22", /* O2 */ 129*724ba675SRob Herring "GPIO167_B24", /* O1 */ 130*724ba675SRob Herring "GPIO168_C22"; /* O0 */ 131*724ba675SRob Herring ste,config = <&out_lo>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring }; 134*724ba675SRob Herring ske_kpa2_sleep_mode: ske_kpa2_sleep { 135*724ba675SRob Herring sleep_cfg1 { 136*724ba675SRob Herring pins = 137*724ba675SRob Herring "GPIO153_B17", /* I7 */ 138*724ba675SRob Herring "GPIO154_C16", /* I6 */ 139*724ba675SRob Herring "GPIO155_C19", /* I5 */ 140*724ba675SRob Herring "GPIO156_C17", /* I4 */ 141*724ba675SRob Herring "GPIO161_D21", /* I3 */ 142*724ba675SRob Herring "GPIO162_D20", /* I2 */ 143*724ba675SRob Herring "GPIO163_C20", /* I1 */ 144*724ba675SRob Herring "GPIO164_B21"; /* I0 */ 145*724ba675SRob Herring ste,config = <&slpm_in_pu_wkup_pdis_en>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring sleep_cfg2 { 148*724ba675SRob Herring pins = 149*724ba675SRob Herring "GPIO157_A18", /* O7 */ 150*724ba675SRob Herring "GPIO158_C18", /* O6 */ 151*724ba675SRob Herring "GPIO159_B19", /* O5 */ 152*724ba675SRob Herring "GPIO160_B20", /* O4 */ 153*724ba675SRob Herring "GPIO165_C21", /* O3 */ 154*724ba675SRob Herring "GPIO166_A22", /* O2 */ 155*724ba675SRob Herring "GPIO167_B24", /* O1 */ 156*724ba675SRob Herring "GPIO168_C22"; /* O0 */ 157*724ba675SRob Herring ste,config = <&slpm_out_lo_pdis>; 158*724ba675SRob Herring }; 159*724ba675SRob Herring }; 160*724ba675SRob Herring /* 161*724ba675SRob Herring * SKE keys on position 1 and "other C1" combi giving 162*724ba675SRob Herring * six rows of six keys. 163*724ba675SRob Herring */ 164*724ba675SRob Herring ske_kpaoc1_default_mode: ske_kpaoc1_default { 165*724ba675SRob Herring default_mux { 166*724ba675SRob Herring function = "kp"; 167*724ba675SRob Herring groups = "kp_a_1", "kp_oc1_1"; 168*724ba675SRob Herring }; 169*724ba675SRob Herring default_cfg1 { 170*724ba675SRob Herring pins = 171*724ba675SRob Herring "GPIO91_B6", /* KP_O0 */ 172*724ba675SRob Herring "GPIO90_A3", /* KP_O1 */ 173*724ba675SRob Herring "GPIO87_B3", /* KP_O2 */ 174*724ba675SRob Herring "GPIO86_C6", /* KP_O3 */ 175*724ba675SRob Herring "GPIO96_D8", /* KP_O6 */ 176*724ba675SRob Herring "GPIO94_D7"; /* KP_O7 */ 177*724ba675SRob Herring ste,config = <&out_lo>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring default_cfg2 { 180*724ba675SRob Herring pins = 181*724ba675SRob Herring "GPIO93_B7", /* KP_I0 */ 182*724ba675SRob Herring "GPIO92_D6", /* KP_I1 */ 183*724ba675SRob Herring "GPIO89_E6", /* KP_I2 */ 184*724ba675SRob Herring "GPIO88_C4", /* KP_I3 */ 185*724ba675SRob Herring "GPIO97_D9", /* KP_I6 */ 186*724ba675SRob Herring "GPIO95_E8"; /* KP_I7 */ 187*724ba675SRob Herring ste,config = <&in_pu>; 188*724ba675SRob Herring }; 189*724ba675SRob Herring }; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring wlan { 193*724ba675SRob Herring wlan_default_mode: wlan_default { 194*724ba675SRob Herring /* 195*724ba675SRob Herring * Activate this mode with the WLAN chip. 196*724ba675SRob Herring * These are plain GPIO pins used by WLAN 197*724ba675SRob Herring */ 198*724ba675SRob Herring default_cfg1 { 199*724ba675SRob Herring pins = 200*724ba675SRob Herring "GPIO226_AF8", /* WLAN_PMU_EN */ 201*724ba675SRob Herring "GPIO85_D5"; /* WLAN_ENA */ 202*724ba675SRob Herring ste,config = <&gpio_out_lo>; 203*724ba675SRob Herring }; 204*724ba675SRob Herring default_cfg2 { 205*724ba675SRob Herring pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ 206*724ba675SRob Herring ste,config = <&gpio_in_pu>; 207*724ba675SRob Herring }; 208*724ba675SRob Herring }; 209*724ba675SRob Herring }; 210*724ba675SRob Herring }; 211*724ba675SRob Herring }; 212*724ba675SRob Herring}; 213