14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-16 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 274562236bSHarry Wentland #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "gpio_regs.h" 304562236bSHarry Wentland 314562236bSHarry Wentland /****************************** new register headers */ 324562236bSHarry Wentland /*** following in header */ 334562236bSHarry Wentland 344562236bSHarry Wentland #define DDC_GPIO_REG_LIST_ENTRY(type, cd, id) \ 354562236bSHarry Wentland .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 364562236bSHarry Wentland .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ 374562236bSHarry Wentland .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT 384562236bSHarry Wentland 394562236bSHarry Wentland #define DDC_GPIO_REG_LIST(cd, id) \ 404562236bSHarry Wentland {\ 414562236bSHarry Wentland DDC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\ 424562236bSHarry Wentland DDC_GPIO_REG_LIST_ENTRY(A, cd, id),\ 434562236bSHarry Wentland DDC_GPIO_REG_LIST_ENTRY(EN, cd, id),\ 444562236bSHarry Wentland DDC_GPIO_REG_LIST_ENTRY(Y, cd, id)\ 454562236bSHarry Wentland } 464562236bSHarry Wentland 474562236bSHarry Wentland #define DDC_REG_LIST(cd, id) \ 484562236bSHarry Wentland DDC_GPIO_REG_LIST(cd, id),\ 494562236bSHarry Wentland .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) 504562236bSHarry Wentland 512e35facfSHarry Wentland #define DDC_REG_LIST_DCN2(cd, id) \ 522e35facfSHarry Wentland DDC_GPIO_REG_LIST(cd, id),\ 532e35facfSHarry Wentland .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ 542e35facfSHarry Wentland .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 552e35facfSHarry Wentland .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 562e35facfSHarry Wentland 574562236bSHarry Wentland #define DDC_GPIO_VGA_REG_LIST_ENTRY(type, cd)\ 584562236bSHarry Wentland .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 594562236bSHarry Wentland .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ 604562236bSHarry Wentland .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT 614562236bSHarry Wentland 624562236bSHarry Wentland #define DDC_GPIO_VGA_REG_LIST(cd) \ 634562236bSHarry Wentland {\ 644562236bSHarry Wentland DDC_GPIO_VGA_REG_LIST_ENTRY(MASK, cd),\ 654562236bSHarry Wentland DDC_GPIO_VGA_REG_LIST_ENTRY(A, cd),\ 664562236bSHarry Wentland DDC_GPIO_VGA_REG_LIST_ENTRY(EN, cd),\ 674562236bSHarry Wentland DDC_GPIO_VGA_REG_LIST_ENTRY(Y, cd)\ 684562236bSHarry Wentland } 694562236bSHarry Wentland 704562236bSHarry Wentland #define DDC_VGA_REG_LIST(cd) \ 714562236bSHarry Wentland DDC_GPIO_VGA_REG_LIST(cd),\ 724562236bSHarry Wentland .ddc_setup = mmDC_I2C_DDCVGA_SETUP 734562236bSHarry Wentland 744562236bSHarry Wentland #define DDC_GPIO_I2C_REG_LIST_ENTRY(type, cd) \ 754562236bSHarry Wentland .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ 764562236bSHarry Wentland .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ 774562236bSHarry Wentland .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT 784562236bSHarry Wentland 794562236bSHarry Wentland #define DDC_GPIO_I2C_REG_LIST(cd) \ 804562236bSHarry Wentland {\ 814562236bSHarry Wentland DDC_GPIO_I2C_REG_LIST_ENTRY(MASK, cd),\ 824562236bSHarry Wentland DDC_GPIO_I2C_REG_LIST_ENTRY(A, cd),\ 834562236bSHarry Wentland DDC_GPIO_I2C_REG_LIST_ENTRY(EN, cd),\ 844562236bSHarry Wentland DDC_GPIO_I2C_REG_LIST_ENTRY(Y, cd)\ 854562236bSHarry Wentland } 864562236bSHarry Wentland 874562236bSHarry Wentland #define DDC_I2C_REG_LIST(cd) \ 884562236bSHarry Wentland DDC_GPIO_I2C_REG_LIST(cd),\ 894562236bSHarry Wentland .ddc_setup = 0 904562236bSHarry Wentland 912e35facfSHarry Wentland #define DDC_I2C_REG_LIST_DCN2(cd) \ 922e35facfSHarry Wentland DDC_GPIO_I2C_REG_LIST(cd),\ 932e35facfSHarry Wentland .ddc_setup = 0,\ 942e35facfSHarry Wentland .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 952e35facfSHarry Wentland .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 96b81e5aa3SCharlene Liu #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ 974562236bSHarry Wentland SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 984562236bSHarry Wentland SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ 994562236bSHarry Wentland SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\ 1004562236bSHarry Wentland SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\ 1014562236bSHarry Wentland SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\ 102b81e5aa3SCharlene Liu SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh) 103b81e5aa3SCharlene Liu 104b81e5aa3SCharlene Liu #define DDC_MASK_SH_LIST(mask_sh) \ 105b81e5aa3SCharlene Liu DDC_MASK_SH_LIST_COMMON(mask_sh),\ 1064562236bSHarry Wentland SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ 1074562236bSHarry Wentland SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) 1084562236bSHarry Wentland 1092e35facfSHarry Wentland #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ 1102e35facfSHarry Wentland {DDC_MASK_SH_LIST_COMMON(mask_sh),\ 1112e35facfSHarry Wentland 0,\ 1122e35facfSHarry Wentland 0,\ 1132e35facfSHarry Wentland (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ 1142e35facfSHarry Wentland (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} 1154562236bSHarry Wentland 116*9190d4a2SBrandon Syu #define DDC_MASK_SH_LIST_DCN2_VGA(mask_sh) \ 117*9190d4a2SBrandon Syu {DDC_MASK_SH_LIST_COMMON(mask_sh),\ 118*9190d4a2SBrandon Syu 0,\ 119*9190d4a2SBrandon Syu 0,\ 120*9190d4a2SBrandon Syu 0,\ 121*9190d4a2SBrandon Syu 0} 122*9190d4a2SBrandon Syu 1234562236bSHarry Wentland struct ddc_registers { 1244562236bSHarry Wentland struct gpio_registers gpio; 1254562236bSHarry Wentland uint32_t ddc_setup; 1262e35facfSHarry Wentland uint32_t phy_aux_cntl; 1272e35facfSHarry Wentland uint32_t dc_gpio_aux_ctrl_5; 1284562236bSHarry Wentland }; 1294562236bSHarry Wentland 1304562236bSHarry Wentland struct ddc_sh_mask { 1314562236bSHarry Wentland /* i2c_dd_setup */ 1324562236bSHarry Wentland uint32_t DC_I2C_DDC1_ENABLE; 1334562236bSHarry Wentland uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; 1344562236bSHarry Wentland uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; 1354562236bSHarry Wentland /* ddc1_mask */ 1364562236bSHarry Wentland uint32_t DC_GPIO_DDC1DATA_PD_EN; 1374562236bSHarry Wentland uint32_t DC_GPIO_DDC1CLK_PD_EN; 1384562236bSHarry Wentland uint32_t AUX_PAD1_MODE; 1394562236bSHarry Wentland /* i2cpad_mask */ 1404562236bSHarry Wentland uint32_t DC_GPIO_SDA_PD_DIS; 1414562236bSHarry Wentland uint32_t DC_GPIO_SCL_PD_DIS; 1422e35facfSHarry Wentland //phy_aux_cntl 1432e35facfSHarry Wentland uint32_t AUX_PAD_RXSEL; 1442e35facfSHarry Wentland uint32_t DDC_PAD_I2CMODE; 1454562236bSHarry Wentland }; 1464562236bSHarry Wentland 1474562236bSHarry Wentland 1484562236bSHarry Wentland 1494562236bSHarry Wentland /*** following in dc_resource */ 1504562236bSHarry Wentland 1514562236bSHarry Wentland #define ddc_data_regs(id) \ 1524562236bSHarry Wentland {\ 1534562236bSHarry Wentland DDC_REG_LIST(DATA, id)\ 1544562236bSHarry Wentland } 1554562236bSHarry Wentland 1564562236bSHarry Wentland #define ddc_clk_regs(id) \ 1574562236bSHarry Wentland {\ 1584562236bSHarry Wentland DDC_REG_LIST(CLK, id)\ 1594562236bSHarry Wentland } 1604562236bSHarry Wentland 1614562236bSHarry Wentland #define ddc_vga_data_regs \ 1624562236bSHarry Wentland {\ 1634562236bSHarry Wentland DDC_VGA_REG_LIST(DATA)\ 1644562236bSHarry Wentland } 1654562236bSHarry Wentland 1664562236bSHarry Wentland #define ddc_vga_clk_regs \ 1674562236bSHarry Wentland {\ 1684562236bSHarry Wentland DDC_VGA_REG_LIST(CLK)\ 1694562236bSHarry Wentland } 1704562236bSHarry Wentland 1714562236bSHarry Wentland #define ddc_i2c_data_regs \ 1724562236bSHarry Wentland {\ 1734562236bSHarry Wentland DDC_I2C_REG_LIST(SDA)\ 1744562236bSHarry Wentland } 1754562236bSHarry Wentland 1764562236bSHarry Wentland #define ddc_i2c_clk_regs \ 1774562236bSHarry Wentland {\ 1784562236bSHarry Wentland DDC_I2C_REG_LIST(SCL)\ 1794562236bSHarry Wentland } 1802e35facfSHarry Wentland #define ddc_data_regs_dcn2(id) \ 1812e35facfSHarry Wentland {\ 1822e35facfSHarry Wentland DDC_REG_LIST_DCN2(DATA, id)\ 1832e35facfSHarry Wentland } 1842e35facfSHarry Wentland 1852e35facfSHarry Wentland #define ddc_clk_regs_dcn2(id) \ 1862e35facfSHarry Wentland {\ 1872e35facfSHarry Wentland DDC_REG_LIST_DCN2(CLK, id)\ 1882e35facfSHarry Wentland } 1892e35facfSHarry Wentland 1902e35facfSHarry Wentland #define ddc_i2c_data_regs_dcn2 \ 1912e35facfSHarry Wentland {\ 1922e35facfSHarry Wentland DDC_I2C_REG_LIST_DCN2(SDA)\ 1932e35facfSHarry Wentland } 1942e35facfSHarry Wentland 1952e35facfSHarry Wentland #define ddc_i2c_clk_regs_dcn2 \ 1962e35facfSHarry Wentland {\ 1972e35facfSHarry Wentland DDC_REG_LIST_DCN2(SCL)\ 1982e35facfSHarry Wentland } 1994562236bSHarry Wentland 2004562236bSHarry Wentland 2014562236bSHarry Wentland #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ 202