| /linux/Documentation/leds/ |
| H A D | leds-mlxcpld.rst | 29 - Bits [3:0]
33 - Bits [7:4]
37 - Bits [3:0]
41 - Bits [7:4]
45 - Bits [3:0]
49 - Bits [7:4]
78 - Bits [3:0]
82 - Bits [3:0]
86 - Bits [3:0]
90 - Bits [7:4]
[all …]
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8183-kukui-krane-sku0.dts | 8 * - Bits 7..4: Panel ID: 0x0 (AUO)
9 * - Bits 3..0: SKU ID: 0x0 (default)
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| H A D | mt8183-kukui-krane-sku176.dts | 8 * - Bits 7..4: Panel ID: 0xb (BOE)
9 * - Bits 3..0: SKU ID: 0x0 (default)
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| /linux/Documentation/translations/zh_CN/arch/riscv/ |
| H A D | boot-image-header.rst | 51 Bits 0:15 次要 版本
52 Bits 16:31 主要 版本
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| /linux/Documentation/i2c/busses/ |
| H A D | i2c-mlxcpld.rst | 29 Bits [6:5] - transaction length. b01 - 72B is supported,
42 Bits [7:1] - the 7bit Address of the I2C device.
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| /linux/Documentation/arch/riscv/ |
| H A D | boot-image-header.rst | 40 Bits 0:15 Minor version
41 Bits 16:31 Major version
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-rgb.rst | 51 Less Than 8 Bits Per Component
76 .. flat-table:: RGB Formats With Less Than 8 Bits Per Component
643 8 Bits Per Component
661 .. flat-table:: RGB Formats With 8 Bits Per Component
767 10 Bits Per Component
785 .. flat-table:: RGB Formats 10 Bits Per Color Component
957 12 Bits Per Component
968 .. flat-table:: RGB Formats With 12 Bits Per Component
1000 16 Bits Per Component
1014 .. flat-table:: RGB Formats With 16 Bits Per Component
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| H A D | pixfmt-cnf4.rst | 21 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
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| H A D | dev-rds.rst | 119 * - Bits 0-2
121 * - Bits 3-5
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-tegra-fuse | 8 as decoded from the fuse registers. Bits order/assignment
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| /linux/Documentation/hwmon/ |
| H A D | tmp103.rst | 26 Resolution: 8 Bits
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| H A D | max31760.rst | 39 Temperature Resolution: 11 Bits, ±0.125°C
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| /linux/Documentation/arch/loongarch/ |
| H A D | introduction.rst | 112 0x11 TLB Entry High-order Bits TLBEHI
113 0x12 TLB Entry Low-order Bits 0 TLBELO0
114 0x13 TLB Entry Low-order Bits 1 TLBELO1
148 Bits 0
150 Bits 1
152 Bits
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | cirrus,clps711x-fb.txt | 11 - bits-per-pixel: Bits per pixel.
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| /linux/Documentation/w1/slaves/ |
| H A D | w1_ds2406.rst | 24 respectively. Bits 2-7 are ignored, so it's safe to write ASCII data.
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| H A D | w1_ds28e04.rst | 40 represent the state of PIO_0/PIO_1. Bits 2..7 do not care. The PIO's are
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| /linux/Documentation/input/devices/ |
| H A D | iforce-protocol.rst | 82 01 Bit 8 is set if the effect is playing. Bits 0 to 7 are the effect id.
111 Bits 4-7: Val 2 = effect along one axis. Byte 05 indicates direction
115 Bits 0-3: Val 0 = No trigger
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| /linux/drivers/media/tuners/ |
| H A D | mt2063.c | 1316 enum MT2063_Mask_Bits Bits) in MT2063_ClearPowerMaskBits() argument
1321 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */ in MT2063_ClearPowerMaskBits()
1322 if ((Bits & 0xFF00) != 0) { in MT2063_ClearPowerMaskBits()
1323 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); in MT2063_ClearPowerMaskBits()
1329 if ((Bits & 0xFF) != 0) { in MT2063_ClearPowerMaskBits()
1330 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); in MT2063_ClearPowerMaskBits()
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| /linux/Documentation/arch/xtensa/ |
| H A D | atomctl.rst | 37 See Section 4.3.12.4 of ISA; Bits::
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| /linux/Documentation/arch/sparc/oradax/ |
| H A D | dax-hv-api.txt | 141 Bits Field Description
182 Bits Field Description
447 Bits Field Description
466 Bits Field Description
476 Bits Field Description
488 Bits Field Description
500 Bits Field Description
517 Bits Field Description
568 Bits Field Description
581 Bits Fiel
[all...] |
| /linux/Documentation/admin-guide/mm/ |
| H A D | pagemap.rst | 16 * Bits 0-54 page frame number (PFN) if present
17 * Bits 0-4 swap type if swapped
18 * Bits 5-54 swap offset if swapped
25 * Bits 59-60 zero
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | msr.rst | 195 Bits 63-6 hold 64-byte aligned physical address of a 64 byte memory area
209 Bits 5-4 of the MSR are reserved and should be zero. Bit 0 is set to 1
359 Bits 0-7: APIC vector for delivery of 'page ready' APF events.
360 Bits 8-63: Reserved
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| /linux/Documentation/devicetree/bindings/powerpc/ |
| H A D | ibm,powerpc-cpu-features.txt | 182 Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond
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| /linux/Documentation/driver-api/media/drivers/ |
| H A D | cx88-devel.rst | 88 Bits are then right shifted into the GP_SAMPLE register at the specified
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| /linux/Documentation/driver-api/cxl/platform/ |
| H A D | acpi.rst | 56 * CEDT CFMWS Restriction Bits are not correct.
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