1*ccf988b6SMauro Carvalho Chehab================== 2*ccf988b6SMauro Carvalho ChehabDriver i2c-mlxcpld 3*ccf988b6SMauro Carvalho Chehab================== 4*ccf988b6SMauro Carvalho Chehab 5*ccf988b6SMauro Carvalho ChehabAuthor: Michael Shych <michaelsh@mellanox.com> 6*ccf988b6SMauro Carvalho Chehab 7*ccf988b6SMauro Carvalho ChehabThis is the Mellanox I2C controller logic, implemented in Lattice CPLD 8*ccf988b6SMauro Carvalho Chehabdevice. 9*ccf988b6SMauro Carvalho Chehab 10*ccf988b6SMauro Carvalho ChehabDevice supports: 11*ccf988b6SMauro Carvalho Chehab - Master mode. 12*ccf988b6SMauro Carvalho Chehab - One physical bus. 13*ccf988b6SMauro Carvalho Chehab - Polling mode. 14*ccf988b6SMauro Carvalho Chehab 15*ccf988b6SMauro Carvalho ChehabThis controller is equipped within the next Mellanox systems: 16*ccf988b6SMauro Carvalho Chehab"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", 17*ccf988b6SMauro Carvalho Chehab"msn2740", "msn2100". 18*ccf988b6SMauro Carvalho Chehab 19*ccf988b6SMauro Carvalho ChehabThe next transaction types are supported: 20*ccf988b6SMauro Carvalho Chehab - Receive Byte/Block. 21*ccf988b6SMauro Carvalho Chehab - Send Byte/Block. 22*ccf988b6SMauro Carvalho Chehab - Read Byte/Block. 23*ccf988b6SMauro Carvalho Chehab - Write Byte/Block. 24*ccf988b6SMauro Carvalho Chehab 25*ccf988b6SMauro Carvalho ChehabRegisters: 26*ccf988b6SMauro Carvalho Chehab 27*ccf988b6SMauro Carvalho Chehab=============== === ======================================================================= 28*ccf988b6SMauro Carvalho ChehabCPBLTY 0x0 - capability reg. 29*ccf988b6SMauro Carvalho Chehab Bits [6:5] - transaction length. b01 - 72B is supported, 30*ccf988b6SMauro Carvalho Chehab 36B in other case. 31*ccf988b6SMauro Carvalho Chehab Bit 7 - SMBus block read support. 32*ccf988b6SMauro Carvalho ChehabCTRL 0x1 - control reg. 33*ccf988b6SMauro Carvalho Chehab Resets all the registers. 34*ccf988b6SMauro Carvalho ChehabHALF_CYC 0x4 - cycle reg. 35*ccf988b6SMauro Carvalho Chehab Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK 36*ccf988b6SMauro Carvalho Chehab units). 37*ccf988b6SMauro Carvalho ChehabI2C_HOLD 0x5 - hold reg. 38*ccf988b6SMauro Carvalho Chehab OE (output enable) is delayed by value set to this register 39*ccf988b6SMauro Carvalho Chehab (in LPC_CLK units) 40*ccf988b6SMauro Carvalho ChehabCMD 0x6 - command reg. 41*ccf988b6SMauro Carvalho Chehab Bit 0, 0 = write, 1 = read. 42*ccf988b6SMauro Carvalho Chehab Bits [7:1] - the 7bit Address of the I2C device. 43*ccf988b6SMauro Carvalho Chehab It should be written last as it triggers an I2C transaction. 44*ccf988b6SMauro Carvalho ChehabNUM_DATA 0x7 - data size reg. 45*ccf988b6SMauro Carvalho Chehab Number of data bytes to write in read transaction 46*ccf988b6SMauro Carvalho ChehabNUM_ADDR 0x8 - address reg. 47*ccf988b6SMauro Carvalho Chehab Number of address bytes to write in read transaction. 48*ccf988b6SMauro Carvalho ChehabSTATUS 0x9 - status reg. 49*ccf988b6SMauro Carvalho Chehab Bit 0 - transaction is completed. 50*ccf988b6SMauro Carvalho Chehab Bit 4 - ACK/NACK. 51*ccf988b6SMauro Carvalho ChehabDATAx 0xa - 0x54 - 68 bytes data buffer regs. 52*ccf988b6SMauro Carvalho Chehab For write transaction address is specified in four first bytes 53*ccf988b6SMauro Carvalho Chehab (DATA1 - DATA4), data starting from DATA4. 54*ccf988b6SMauro Carvalho Chehab For read transactions address is sent in a separate transaction and 55*ccf988b6SMauro Carvalho Chehab specified in the four first bytes (DATA0 - DATA3). Data is read 56*ccf988b6SMauro Carvalho Chehab starting from DATA0. 57*ccf988b6SMauro Carvalho Chehab=============== === ======================================================================= 58