/linux/arch/loongarch/include/asm/ |
H A D | asmmacro.h | 42 .macro fpu_save_csr thread tmp 43 movfcsr2gr \tmp, fcsr0 44 stptr.w \tmp, \thread, THREAD_FCSR 47 andi \tmp, \tmp, FPU_CSR_TM 48 beqz \tmp, 1f 50 x86mftop \tmp 51 stptr.w \tmp, \thread, THREAD_FTOP 131 .macro fpu_save_double thread tmp 132 li.w \tmp, THREAD_FPR0 133 PTR_ADD \tmp, \tmp, \thread [all …]
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | mmhub_v3_3.c | 168 uint32_t tmp; in mmhub_v3_3_init_system_aperture_regs() local 199 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_3_init_system_aperture_regs() 200 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_3_init_system_aperture_regs() 202 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_3_init_system_aperture_regs() 207 uint32_t tmp; in mmhub_v3_3_init_tlb_regs() local 210 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_init_tlb_regs() 212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_3_init_tlb_regs() 213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_3_init_tlb_regs() 214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_3_init_tlb_regs() 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_3_init_tlb_regs() [all …]
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H A D | mmhub_v3_0_2.c | 163 uint32_t tmp; in mmhub_v3_0_2_init_system_aperture_regs() local 196 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_2_init_system_aperture_regs() 197 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_2_init_system_aperture_regs() 199 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_2_init_system_aperture_regs() 204 uint32_t tmp; in mmhub_v3_0_2_init_tlb_regs() local 207 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_init_tlb_regs() 209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_2_init_tlb_regs() 210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_2_init_tlb_regs() 211 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_2_init_tlb_regs() 213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_2_init_tlb_regs() [all …]
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H A D | gfxhub_v3_0_3.c | 191 uint32_t tmp; in gfxhub_v3_0_3_init_tlb_regs() local 194 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_3_init_tlb_regs() 196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs() 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_3_init_tlb_regs() 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs() 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs() 202 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_3_init_tlb_regs() 203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs() 206 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_3_init_tlb_regs() 211 uint32_t tmp; in gfxhub_v3_0_3_init_cache_regs() local [all …]
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H A D | gfxhub_v2_0.c | 188 uint32_t tmp; in gfxhub_v2_0_init_tlb_regs() local 191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs() 193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs() 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs() 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs() 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs() 199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs() 202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs() 207 uint32_t tmp; in gfxhub_v2_0_init_cache_regs() local 214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs() [all …]
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H A D | gfxhub_v11_5_0.c | 189 uint32_t tmp; in gfxhub_v11_5_0_init_tlb_regs() local 192 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v11_5_0_init_tlb_regs() 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v11_5_0_init_tlb_regs() 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v11_5_0_init_tlb_regs() 196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v11_5_0_init_tlb_regs() 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v11_5_0_init_tlb_regs() 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v11_5_0_init_tlb_regs() 201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v11_5_0_init_tlb_regs() 204 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v11_5_0_init_tlb_regs() 209 uint32_t tmp; in gfxhub_v11_5_0_init_cache_regs() local [all …]
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H A D | gfxhub_v3_0.c | 186 uint32_t tmp; in gfxhub_v3_0_init_tlb_regs() local 189 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_init_tlb_regs() 191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs() 192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_init_tlb_regs() 193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs() 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs() 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_init_tlb_regs() 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs() 201 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_init_tlb_regs() 206 uint32_t tmp; in gfxhub_v3_0_init_cache_regs() local [all …]
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H A D | gfxhub_v12_0.c | 194 uint32_t tmp; in gfxhub_v12_0_init_tlb_regs() local 197 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v12_0_init_tlb_regs() 199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v12_0_init_tlb_regs() 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v12_0_init_tlb_regs() 201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v12_0_init_tlb_regs() 203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v12_0_init_tlb_regs() 205 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v12_0_init_tlb_regs() 206 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v12_0_init_tlb_regs() 209 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v12_0_init_tlb_regs() 214 uint32_t tmp; in gfxhub_v12_0_init_cache_regs() local [all …]
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H A D | mmhub_v3_0_1.c | 172 uint32_t tmp; in mmhub_v3_0_1_init_system_aperture_regs() local 203 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs() 204 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_1_init_system_aperture_regs() 206 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_1_init_system_aperture_regs() 211 uint32_t tmp; in mmhub_v3_0_1_init_tlb_regs() local 214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs() 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_1_init_tlb_regs() 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_1_init_tlb_regs() 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_1_init_tlb_regs() 220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_1_init_tlb_regs() [all …]
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H A D | mmhub_v3_0.c | 170 uint32_t tmp; in mmhub_v3_0_init_system_aperture_regs() local 204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs() 205 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v3_0_init_system_aperture_regs() 207 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v3_0_init_system_aperture_regs() 212 uint32_t tmp; in mmhub_v3_0_init_tlb_regs() local 215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs() 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_init_tlb_regs() 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v3_0_init_tlb_regs() 219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_init_tlb_regs() 221 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v3_0_init_tlb_regs() [all …]
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H A D | mmhub_v4_1_0.c | 170 uint32_t tmp; in mmhub_v4_1_0_init_system_aperture_regs() local 205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v4_1_0_init_system_aperture_regs() 206 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v4_1_0_init_system_aperture_regs() 208 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v4_1_0_init_system_aperture_regs() 213 uint32_t tmp; in mmhub_v4_1_0_init_tlb_regs() local 216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs() 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v4_1_0_init_tlb_regs() 219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v4_1_0_init_tlb_regs() 220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v4_1_0_init_tlb_regs() 222 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v4_1_0_init_tlb_regs() [all …]
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H A D | mmhub_v2_3.c | 153 uint32_t tmp; in mmhub_v2_3_init_system_aperture_regs() local 179 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs() 180 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_3_init_system_aperture_regs() 182 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_3_init_system_aperture_regs() 187 uint32_t tmp; in mmhub_v2_3_init_tlb_regs() local 190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs() 192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs() 193 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_3_init_tlb_regs() 194 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_3_init_tlb_regs() 196 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_3_init_tlb_regs() [all …]
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H A D | mmhub_v2_0.c | 221 uint32_t tmp; in mmhub_v2_0_init_system_aperture_regs() local 249 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs() 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs() 252 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_0_init_system_aperture_regs() 257 uint32_t tmp; in mmhub_v2_0_init_tlb_regs() local 260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs() 262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs() 263 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_0_init_tlb_regs() 264 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs() 266 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs() [all …]
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H A D | lsdma_v7_0.c | 45 uint32_t tmp; in lsdma_v7_0_copy_mem() local 55 tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); in lsdma_v7_0_copy_mem() 56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v7_0_copy_mem() 57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v7_0_copy_mem() 58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v7_0_copy_mem() 59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v7_0_copy_mem() 60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v7_0_copy_mem() 61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v7_0_copy_mem() 62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v7_0_copy_mem() 63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); in lsdma_v7_0_copy_mem() [all …]
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H A D | lsdma_v6_0.c | 45 uint32_t tmp; in lsdma_v6_0_copy_mem() local 55 tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); in lsdma_v6_0_copy_mem() 56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_copy_mem() 57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_copy_mem() 58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_copy_mem() 59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v6_0_copy_mem() 60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v6_0_copy_mem() 61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v6_0_copy_mem() 62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v6_0_copy_mem() 63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); in lsdma_v6_0_copy_mem() [all …]
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H A D | mmhub_v1_0.c | 88 uint32_t tmp; in mmhub_v1_0_init_system_aperture_regs() local 131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs() 132 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs() 134 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_0_init_system_aperture_regs() 139 uint32_t tmp; in mmhub_v1_0_init_tlb_regs() local 142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs() 144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs() 145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs() 146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs() 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs() [all …]
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H A D | gfxhub_v2_1.c | 192 uint32_t tmp; in gfxhub_v2_1_init_tlb_regs() local 195 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs() 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs() 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_1_init_tlb_regs() 199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs() 201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs() 203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs() 206 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_init_tlb_regs() 211 uint32_t tmp; in gfxhub_v2_1_init_cache_regs() local 220 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs() [all …]
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H A D | gmc_v8_0.c | 191 u32 tmp; in gmc_v8_0_mc_resume() local 194 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume() 195 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume() 196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume() 198 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume() 199 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume() 200 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume() 429 u32 tmp; in gmc_v8_0_mc_program() local 447 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program() 448 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program() [all …]
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/linux/drivers/gpu/drm/radeon/ |
H A D | radeon_clocks.c | 200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local 203 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info() 205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info() 393 uint32_t tmp; in radeon_legacy_set_engine_clock() local 400 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock() 401 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock() 402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock() 404 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock() 405 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock() 406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock() [all …]
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H A D | vce_v2_0.c | 41 u32 tmp; in vce_v2_0_set_sw_cg() local 44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg() 45 tmp |= 0xe70000; in vce_v2_0_set_sw_cg() 46 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg() 48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg() 49 tmp |= 0xff000000; in vce_v2_0_set_sw_cg() 50 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg() 52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg() 53 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg() 54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg() [all …]
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/linux/drivers/scsi/mvsas/ |
H A D | mv_64xx.c | 31 u32 tmp; in mvs_64xx_enable_xmt() local 33 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt() 35 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt() 37 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt() 38 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt() 70 u32 reg, tmp; in mvs_64xx_stp_reset() local 81 tmp = reg; in mvs_64xx_stp_reset() 83 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset() 85 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset() 89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset() [all …]
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/linux/drivers/video/fbdev/kyro/ |
H A D | STG4000Ramdac.c | 29 u32 tmp = 0; in InitialiseRamdac() local 35 tmp = STG_READ_REG(SoftwareReset); in InitialiseRamdac() 37 if (tmp & 0x1) { in InitialiseRamdac() 39 STG_WRITE_REG(SoftwareReset, tmp); in InitialiseRamdac() 43 tmp = STG_READ_REG(DACPixelFormat); in InitialiseRamdac() 53 tmp |= _16BPP; in InitialiseRamdac() 60 tmp |= _32BPP; in InitialiseRamdac() 67 STG_WRITE_REG(DACPixelFormat, tmp); in InitialiseRamdac() 76 tmp = STG_READ_REG(DACPrimSize); in InitialiseRamdac() 79 tmp |= in InitialiseRamdac() [all …]
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H A D | STG4000OverlayDevice.c | 81 u32 tmp; in ResetOverlayRegisters() local 84 tmp = STG_READ_REG(DACOverlayAddr); in ResetOverlayRegisters() 87 STG_WRITE_REG(DACOverlayAddr, tmp); in ResetOverlayRegisters() 90 tmp = STG_READ_REG(DACOverlayUAddr); in ResetOverlayRegisters() 92 STG_WRITE_REG(DACOverlayUAddr, tmp); in ResetOverlayRegisters() 95 tmp = STG_READ_REG(DACOverlayVAddr); in ResetOverlayRegisters() 97 STG_WRITE_REG(DACOverlayVAddr, tmp); in ResetOverlayRegisters() 100 tmp = STG_READ_REG(DACOverlaySize); in ResetOverlayRegisters() 103 STG_WRITE_REG(DACOverlaySize, tmp); in ResetOverlayRegisters() 106 tmp = STG4000_NO_DECIMATION; in ResetOverlayRegisters() [all …]
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/linux/drivers/pnp/isapnp/ |
H A D | core.c | 352 unsigned char tag, tmp[2]; in isapnp_read_tag() local 359 isapnp_peek(tmp, 2); in isapnp_read_tag() 360 *size = (tmp[1] << 8) | tmp[0]; in isapnp_read_tag() 384 unsigned char tmp[6]; in isapnp_parse_device() local 389 isapnp_peek(tmp, size); in isapnp_parse_device() 390 eisa_id = tmp[0] | tmp[1] << 8 | tmp[2] << 16 | tmp[3] << 24; in isapnp_parse_device() 413 unsigned char tmp[3]; in isapnp_parse_irq_resource() local 418 isapnp_peek(tmp, size); in isapnp_parse_irq_resource() 419 bits = (tmp[1] << 8) | tmp[0]; in isapnp_parse_irq_resource() 425 flags = tmp[2]; in isapnp_parse_irq_resource() [all …]
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/linux/arch/csky/kernel/probes/ |
H A D | simulate-insn.c | 125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16() local 127 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp16() 129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16() 135 unsigned long tmp = opcode & 0x1f; in simulate_jmp32() local 137 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp32() 139 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp32() 145 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jsr16() local 147 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jsr16() 151 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jsr16() 157 unsigned long tmp = opcode & 0x1f; in simulate_jsr32() local [all …]
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