Lines Matching refs:tmp
186 uint32_t tmp; in gfxhub_v3_0_init_tlb_regs() local
189 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_init_tlb_regs()
191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_init_tlb_regs()
201 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_init_tlb_regs()
206 uint32_t tmp; in gfxhub_v3_0_init_cache_regs() local
215 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_init_cache_regs()
216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v3_0_init_cache_regs()
218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_init_cache_regs()
221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_init_cache_regs()
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v3_0_init_cache_regs()
224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v3_0_init_cache_regs()
225 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v3_0_init_cache_regs()
226 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_init_cache_regs()
228 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_init_cache_regs()
229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_init_cache_regs()
230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_init_cache_regs()
233 tmp = regGCVM_L2_CNTL3_DEFAULT; in gfxhub_v3_0_init_cache_regs()
235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v3_0_init_cache_regs()
236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v3_0_init_cache_regs()
240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_init_cache_regs()
243 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_init_cache_regs()
245 tmp = regGCVM_L2_CNTL4_DEFAULT; in gfxhub_v3_0_init_cache_regs()
246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); in gfxhub_v3_0_init_cache_regs()
247 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); in gfxhub_v3_0_init_cache_regs()
248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v3_0_init_cache_regs()
250 tmp = regGCVM_L2_CNTL5_DEFAULT; in gfxhub_v3_0_init_cache_regs()
251 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); in gfxhub_v3_0_init_cache_regs()
252 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_init_cache_regs()
257 uint32_t tmp; in gfxhub_v3_0_enable_system_domain() local
259 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_enable_system_domain()
260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_enable_system_domain()
261 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v3_0_enable_system_domain()
262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v3_0_enable_system_domain()
264 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v3_0_enable_system_domain()
294 uint32_t tmp; in gfxhub_v3_0_setup_vmid_config() local
297 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); in gfxhub_v3_0_setup_vmid_config()
298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_setup_vmid_config()
299 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v3_0_setup_vmid_config()
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
319 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
323 i * hub->ctx_distance, tmp); in gfxhub_v3_0_setup_vmid_config()
336 hub->vm_cntx_cntl = tmp; in gfxhub_v3_0_setup_vmid_config()
383 u32 tmp; in gfxhub_v3_0_gart_disable() local
392 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_gart_disable()
393 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v3_0_gart_disable()
394 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_gart_disable()
396 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_gart_disable()
412 u32 tmp; in gfxhub_v3_0_set_fault_enable_default() local
415 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v3_0_set_fault_enable_default()
416 tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1); in gfxhub_v3_0_set_fault_enable_default()
417 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v3_0_set_fault_enable_default()
425 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_set_fault_enable_default()
426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
434 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
445 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
447 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
450 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
452 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_set_fault_enable_default()
455 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_set_fault_enable_default()