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/linux/drivers/clk/berlin/
H A Dberlin2-div.c67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
68 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
71 if (div->lock) in berlin2_div_is_enabled()
72 spin_lock(div->lock); in berlin2_div_is_enabled()
74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
78 spin_unlock(div->lock); in berlin2_div_is_enabled()
85 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
86 struct berlin2_div_map *map = &div->map; in berlin2_div_enable()
89 if (div->lock) in berlin2_div_enable()
[all …]
/linux/drivers/clk/ti/
H A Ddivider.c26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
28 return clkt->div; in _get_table_div()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
72 unsigned int div) in _get_table_val() argument
76 for (clkt = table; clkt->div; clkt++) in _get_table_val()
77 if (clkt->div == div) in _get_table_val()
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
85 return div; in _get_val()
87 return __ffs(div); in _get_val()
89 return _get_table_val(divider->table, div); in _get_val()
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/linux/drivers/clk/imx/
H A Dclk-divider-gate.c21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
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/linux/drivers/clk/
H A Dclk-divider.c52 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
53 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
54 maxdiv = clkt->div; in _get_table_maxdiv()
63 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
64 if (clkt->div < mindiv) in _get_table_mindiv()
65 mindiv = clkt->div; in _get_table_mindiv()
88 for (clkt = table; clkt->div; clkt++) in _get_table_div()
90 return clkt->div; in _get_table_div()
111 unsigned int div) in _get_table_val() argument
115 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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H A Dclk-fsl-flexspi.c14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
22 { .val = 11, .div = 12, },
23 { .val = 15, .div = 16, },
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H A Dclk-milbeaut.c83 u8 div; member
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div = 4 },
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H A Dclk-cdce706.c28 #define CDCE706_DIVIDER(div) (13 + (div)) argument
49 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
50 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
51 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
71 unsigned div; member
169 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
172 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
175 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
179 if (hwd->div) in cdce706_pll_recalc_rate()
180 return parent_rate / hwd->div; in cdce706_pll_recalc_rate()
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H A Dclk-bm1880.c98 struct bm1880_div_clock div; member
184 .div.id = _id, \
185 .div.name = _name, \
186 .div.reg = _reg, \
187 .div.shift = _shift, \
188 .div.width = _width, \
189 .div.initval = _initval, \
190 .div.table = _table, \
592 struct bm1880_div_clock *div = &div_hw->div; in bm1880_clk_div_recalc_rate() local
593 void __iomem *reg_addr = div_hw->base + div->reg; in bm1880_clk_div_recalc_rate()
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/linux/drivers/clk/mxs/
H A Dclk-div.c38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_determine_rate() local
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc_obj(*div); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
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/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
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H A Dclk-sun9i-cpus.c33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
34 (div << SUN9I_CPUS_DIV_SHIFT))
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
40 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
72 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
81 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
84 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
86 if (div < 32) { in sun9i_a80_cpus_clk_round()
87 pre_div = div; in sun9i_a80_cpus_clk_round()
88 div = 1; in sun9i_a80_cpus_clk_round()
[all …]
/linux/drivers/clk/bcm/
H A Dclk-iproc-asiu.c22 struct iproc_asiu_div div; member
81 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
82 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
88 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
90 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
103 unsigned int div; in iproc_asiu_clk_determine_rate() local
111 div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); in iproc_asiu_clk_determine_rate()
112 if (div < 2) { in iproc_asiu_clk_determine_rate()
118 req->rate = req->best_parent_rate / div; in iproc_asiu_clk_determine_rate()
128 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
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H A Dclk-kona.c51 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value() argument
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
58 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min() argument
60 if (divider_is_fixed(div)) in scaled_div_min()
61 return (u64)div->u.fixed; in scaled_div_min()
63 return scaled_div_value(div, 0); in scaled_div_min()
67 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max() argument
71 if (divider_is_fixed(div)) in scaled_div_max()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
[all …]
/linux/drivers/clk/ingenic/
H A Dcgu.c414 u32 div_reg, div; in ingenic_clk_recalc_rate() local
420 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
421 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
422 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
423 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
425 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
426 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
428 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
430 rate /= div; in ingenic_clk_recalc_rate()
433 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
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/linux/drivers/clk/tegra/
H A Dclk-divider.c24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
55 rate += div - 1; in clk_frac_div_recalc_rate()
56 do_div(rate, div); in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_determine_rate() local
[all …]
/linux/drivers/clk/zynqmp/
H A Ddivider.c86 u32 div, value; in zynqmp_clk_divider_recalc_rate() local
89 ret = zynqmp_pm_clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
96 value = div & 0xFFFF; in zynqmp_clk_divider_recalc_rate()
98 value = div >> 16; in zynqmp_clk_divider_recalc_rate()
179 u32 value, div; in zynqmp_clk_divider_set_rate() local
184 div = value & 0xFFFF; in zynqmp_clk_divider_set_rate()
185 div |= 0xffff << 16; in zynqmp_clk_divider_set_rate()
187 div = 0xffff; in zynqmp_clk_divider_set_rate()
188 div |= value << 16; in zynqmp_clk_divider_set_rate()
192 div = __ffs(div); in zynqmp_clk_divider_set_rate()
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/linux/drivers/media/platform/st/sti/hva/
H A Dhva-debugfs.c121 u64 div; in hva_dbg_perf_begin() local
131 div = (u64)ktime_us_delta(dbg->begin, prev); in hva_dbg_perf_begin()
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
152 div = (u64)dbg->window_stream_size * 80; in hva_dbg_perf_begin()
153 do_div(div, dbg->window_duration); in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
187 div = stream->vbuf.vb2_buf.timestamp; in hva_dbg_perf_end()
188 do_div(div, 1000); in hva_dbg_perf_end()
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/linux/drivers/clk/sunxi-ng/
H A Dccu_div.c23 if (cd->div.flags & CLK_DIVIDER_READ_ONLY) { in ccu_div_determine_rate_helper()
28 val = reg >> cd->div.shift; in ccu_div_determine_rate_helper()
29 val &= (1 << cd->div.width) - 1; in ccu_div_determine_rate_helper()
31 ret = divider_ro_determine_rate(&cd->common.hw, req, cd->div.table, in ccu_div_determine_rate_helper()
32 cd->div.width, cd->div.flags, val); in ccu_div_determine_rate_helper()
35 ret = divider_determine_rate(&cd->common.hw, req, cd->div.table, in ccu_div_determine_rate_helper()
36 cd->div.width, cd->div.flags); in ccu_div_determine_rate_helper()
77 val = reg >> cd->div.shift; in ccu_div_recalc_rate()
78 val &= (1 << cd->div.width) - 1; in ccu_div_recalc_rate()
83 val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, in ccu_div_recalc_rate()
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/linux/drivers/clk/qcom/
H A Dclk-regmap-mux-div.c23 int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) in mux_div_set_src_div() argument
29 val = (div << md->hid_shift) | (src << md->src_shift); in mux_div_set_src_div()
60 u32 *div) in mux_div_get_src_div() argument
79 *div = d; in mux_div_get_src_div()
92 unsigned int i, div, max_div; in mux_div_determine_rate() local
101 for (div = 1; div < max_div; div++) { in mux_div_determine_rate()
102 parent_rate = mult_frac(req_rate, div, 2); in mux_div_determine_rate()
104 actual_rate = mult_frac(parent_rate, 2, div); in mux_div_determine_rate()
129 u32 div, max_div, best_src = 0, best_div = 0; in __mux_div_set_rate_and_parent() local
138 for (div = 1; div < max_div; div++) { in __mux_div_set_rate_and_parent()
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/linux/Documentation/sphinx-static/
H A Dcustom.css6 div.body { max-width: 120em; }
9 div.body h1 { font-size: 180%; }
10 div.body h2 { font-size: 150%; }
11 div.body h3 { font-size: 130%; }
12 div.body h4 { font-size: 110%; }
15 div.toctree-wrapper p.caption[role=heading] { font-size: 150%; }
18 div.body { padding: 0 15px 0 10px; }
19 div.sphinxsidebarwrapper { padding: 1em 0.4em; }
20 div.sphinxsidebar { font-size: inherit;
24 div.document {
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/linux/sound/aoa/soundbus/i2sbus/
H A Dinterface.h89 # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK) argument
90 static inline int i2s_sf_mclkdiv(int div, int *out) in i2s_sf_mclkdiv() argument
94 switch(div) { in i2s_sf_mclkdiv()
100 if (div%2) return -1; in i2s_sf_mclkdiv()
101 d = div/2-1; in i2s_sf_mclkdiv()
104 *out |= I2S_SF_MCLKDIV_OTHER(div); in i2s_sf_mclkdiv()
116 # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK) argument
117 static inline int i2s_sf_sclkdiv(int div, int *out) in i2s_sf_sclkdiv() argument
121 switch(div) { in i2s_sf_sclkdiv()
125 if (div%2) return -1; in i2s_sf_sclkdiv()
[all …]
/linux/drivers/clk/actions/
H A Dowl-factor.c21 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
28 unsigned int val, unsigned int *mul, unsigned int *div) in _get_table_div_mul() argument
32 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
35 *div = clkt->div; in _get_table_div_mul()
50 for (clkt = table; clkt->div; clkt++) { in _get_table_val()
52 do_div(calc_rate, clkt->div); in _get_table_val()
84 for (clkt = factor_hw->table; clkt->div; clkt++) { in owl_clk_val_best()
85 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
89 __func__, clkt->val, clkt->mul, clkt->div, in owl_clk_val_best()
102 cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul; in owl_clk_val_best()
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/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c104 struct hi6220_clk_divider *div; in hi6220_register_clkdiv() local
116 div = kzalloc_flex(*div, table, max_div + 1); in hi6220_register_clkdiv()
117 if (!div) in hi6220_register_clkdiv()
121 table = &div->table[i]; in hi6220_register_clkdiv()
122 table->div = min_div + i; in hi6220_register_clkdiv()
123 table->val = table->div - 1; in hi6220_register_clkdiv()
133 div->reg = reg; in hi6220_register_clkdiv()
134 div->shift = shift; in hi6220_register_clkdiv()
135 div->width = width; in hi6220_register_clkdiv()
136 div->mask = mask_bit ? BIT(mask_bit) : 0; in hi6220_register_clkdiv()
[all …]
/linux/drivers/clk/at91/
H A Dclk-master.c39 u8 div; member
87 u8 div; in clk_master_div_recalc_rate() local
101 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_recalc_rate()
103 rate /= characteristics->divisors[div]; in clk_master_div_recalc_rate()
118 unsigned int mckr, div; in clk_master_div_save_context() local
125 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_save_context()
126 div = master->characteristics->divisors[div]; in clk_master_div_save_context()
129 master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); in clk_master_div_save_context()
139 u8 div; in clk_master_div_restore_context() local
146 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_restore_context()
[all …]
H A Dclk-sam9x60-pll.c47 u8 div; member
346 static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, in sam9x60_div_pll_set_div() argument
355 (div << core->layout->div_shift) | ena_val); in sam9x60_div_pll_set_div()
367 struct sam9x60_div *div = to_sam9x60_div(core); in sam9x60_div_pll_set() local
379 if (!!(val & core->layout->endiv_mask) && cdiv == div->div) in sam9x60_div_pll_set()
382 sam9x60_div_pll_set_div(core, div->div, 1); in sam9x60_div_pll_set()
440 struct sam9x60_div *div = to_sam9x60_div(core); in sam9x60_div_pll_recalc_rate() local
442 return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); in sam9x60_div_pll_recalc_rate()
509 struct sam9x60_div *div = to_sam9x60_div(core); in sam9x60_div_pll_set_rate() local
511 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate()
[all …]

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