Lines Matching refs:div
33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
34 (div << SUN9I_CPUS_DIV_SHIFT))
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
40 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
72 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
81 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
84 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
86 if (div < 32) { in sun9i_a80_cpus_clk_round()
87 pre_div = div; in sun9i_a80_cpus_clk_round()
88 div = 1; in sun9i_a80_cpus_clk_round()
89 } else if (div < 64) { in sun9i_a80_cpus_clk_round()
90 pre_div = DIV_ROUND_UP(div, 2); in sun9i_a80_cpus_clk_round()
91 div = 2; in sun9i_a80_cpus_clk_round()
92 } else if (div < 96) { in sun9i_a80_cpus_clk_round()
93 pre_div = DIV_ROUND_UP(div, 3); in sun9i_a80_cpus_clk_round()
94 div = 3; in sun9i_a80_cpus_clk_round()
96 pre_div = DIV_ROUND_UP(div, 4); in sun9i_a80_cpus_clk_round()
97 div = 4; in sun9i_a80_cpus_clk_round()
103 *divp = div - 1; in sun9i_a80_cpus_clk_round()
107 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
154 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
163 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); in sun9i_a80_cpus_clk_set_rate()
165 reg = SUN9I_CPUS_DIV_SET(reg, div); in sun9i_a80_cpus_clk_set_rate()