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Searched refs:phy_addr (Results 1 – 25 of 45) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/
H A Dbnx_hw_phy.c38 u32_t phy_addr, in lm_mwrite() argument
58 tmp = (phy_addr << 21) | in lm_mwrite()
111 u32_t phy_addr, in lm_mread() argument
131 val = (phy_addr << 21) | in lm_mread()
296 (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); in init_utp()
301 (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &val); in init_utp()
314 (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID1_REG, &val); in init_utp()
318 (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID2_REG, &val); in init_utp()
331 (void) lm_mwrite(pdev, pdev->params.phy_addr, 28, 0x3044); in init_utp()
332 (void) lm_mwrite(pdev, pdev->params.phy_addr, 29, 0x0100); in init_utp()
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H A Dbnx_lm_recv.c47 u64_t phy_addr, in post_bd_buffer() argument
71 cur_bd->rx_bd_haddr_lo = ((lm_u64_t *)&phy_addr)->as_u32.low; in post_bd_buffer()
72 cur_bd->rx_bd_haddr_hi = ((lm_u64_t *)&phy_addr)->as_u32.high; in post_bd_buffer()
/illumos-gate/usr/src/uts/common/io/bnx/
H A Dbnxtmr.c53 (void) lm_mwrite(lmdevice, lmdevice->params.phy_addr, in bnx_link_check()
55 (void) lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_link_check()
57 (void) lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_link_check()
62 lmdevice->params.phy_addr, in bnx_link_check()
77 u32_t phy_addr; in bnx_link_check2() local
79 phy_addr = lmdevice->params.phy_addr; in bnx_link_check2()
82 (void) lm_mwrite(lmdevice, phy_addr, 0x1c, 0x6800); in bnx_link_check2()
83 (void) lm_mread(lmdevice, phy_addr, 0x1c, &val); in bnx_link_check2()
84 (void) lm_mread(lmdevice, phy_addr, 0x1c, &val); in bnx_link_check2()
88 (void) lm_mwrite(lmdevice, phy_addr, 0x17, 0x0f03); in bnx_link_check2()
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H A Dbnx_mm.c555 lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_update_lp_cap()
563 lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_update_lp_cap()
584 lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_update_lp_cap()
596 lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_update_lp_cap()
646 lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, in bnx_update_lp_cap()
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dsis900.c83 static void sis900_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
84 static void amd79c901_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
85 static void ics1893_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
86 static void rtl8201_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
87 static void vt6103_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
93 void (*read_mode) (struct nic *nic, int phy_addr, int *speed, int *duplex);
108 int phy_addr; member
321 int phy_addr; in sis900_probe() local
373 for (phy_addr = 0; phy_addr < 32; phy_addr++) { in sis900_probe()
377 mii_status = sis900_mdio_read(phy_addr, MII_STATUS); in sis900_probe()
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H A Ddavicom.c210 int i, phy_addr=1; in phy_read() local
232 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); in phy_read()
255 u16 i, phy_addr=1; in phy_write() local
276 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); in phy_write()
/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dcphy.h33 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
35 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
90 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
92 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
124 int phy_addr, struct cphy_ops *phy_ops, in cphy_init() argument
128 phy->addr = phy_addr; in cphy_init()
139 struct cphy *(*create)(adapter_t *adapter, int phy_addr,
H A Dch_subr.c274 static int fpga_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, in fpga_mdio_read() argument
287 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr)); in fpga_mdio_read()
293 static int fpga_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, in fpga_mdio_write() argument
306 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr)); in fpga_mdio_write()
357 static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, in mi1_mdio_read() argument
360 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); in mi1_mdio_read()
375 static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, in mi1_mdio_write() argument
378 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); in mi1_mdio_write()
404 static int mi1_mdio_ext_readinc(adapter_t *adapter, int phy_addr, int mmd_addr,
407 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
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H A Dmv88x201x.c216 static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr, in mv88x201x_phy_create() argument
225 cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops); in mv88x201x_phy_create()
H A Dmy3126.c205 static struct cphy *my3126_phy_create(adapter_t *adapter, int phy_addr, in my3126_phy_create() argument
211 cphy_init(cphy, adapter, phy_addr, &my3126_ops, mdio_ops); in my3126_phy_create()
H A Dxpak.c108 static struct cphy *xpak_phy_create(adapter_t * adapter, int phy_addr, in xpak_phy_create() argument
H A Dmv88e1xxx.c395 static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr, in mv88e1xxx_phy_create() argument
402 cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops); in mv88e1xxx_phy_create()
/illumos-gate/usr/src/uts/common/io/cpqary3/
H A Dcpqary3_talk2ctlr.c441 uint32_t phy_addr; in cpqary3_init_ctlr() local
684 phy_addr = 0; in cpqary3_init_ctlr()
686 cmd_size, &phy_addr, cpqary3_phyctgp); in cpqary3_init_ctlr()
702 cpqary3p->drvr_replyq->replyq_start_paddr = phy_addr; in cpqary3_init_ctlr()
704 DDI_PUT32_CP(cpqary3p, &perf_cfg->ReplyQAddr0Low32, phy_addr); in cpqary3_init_ctlr()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dbnxe_context.c577 lm_address_t phy_addr = {{0}} ; in lm_allocate_cid() local
649 phy_addr.as_u32.low = (pdev->hw_info.mem_base[BAR_1].as_u32.low) & 0xfffffff0; in lm_allocate_cid()
650 phy_addr.as_u32.high = pdev->hw_info.mem_base[BAR_1].as_u32.high; in lm_allocate_cid()
652 LM_INC64(&phy_addr,(cid*LM_DQ_CID_SIZE)); in lm_allocate_cid()
662 phy_addr, in lm_allocate_cid()
675 (volatile void *)mm_map_io_space(pdev, phy_addr, LM_DQ_CID_SIZE); in lm_allocate_cid()
683 …d: mm_map_io_space failed. address low=%d address high=%d\n", phy_addr.as_u32.low,phy_addr.as_u32.… in lm_allocate_cid()
H A Dlm_phy.c263 tmp = (pdev->vars.phy_addr << 21) | (reg << 16) | (val & EMAC_MDIO_COMM_DATA) | in lm_mwrite()
337 val = (pdev->vars.phy_addr << 21) | (reg << 16) | in lm_mread()
390 u8_t phy_addr, in lm_phy45_read() argument
401 rc = elink_phy_read(&pdev->params.link, phy_addr, dev_addr, reg, ret_val); in lm_phy45_read()
418 u8_t phy_addr, in lm_phy45_write() argument
429 rc = elink_phy_write(&pdev->params.link, phy_addr, dev_addr, reg, val); in lm_phy45_write()
447 pdev->vars.phy_addr = addr; in lm_set_phy_addr()
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_phy.c292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) in ixgbe_probe_phy() argument
296 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { in ixgbe_probe_phy()
298 phy_addr); in ixgbe_probe_phy()
330 u16 phy_addr; in ixgbe_identify_phy_generic() local
345 phy_addr = (hw->phy.nw_mng_if_sel & in ixgbe_identify_phy_generic()
348 if (ixgbe_probe_phy(hw, phy_addr)) in ixgbe_identify_phy_generic()
354 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { in ixgbe_identify_phy_generic()
355 if (ixgbe_probe_phy(hw, phy_addr)) { in ixgbe_identify_phy_generic()
406 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) in ixgbe_validate_phy_addr() argument
413 hw->phy.addr = phy_addr; in ixgbe_validate_phy_addr()
H A Dixgbe_phy.h161 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc.h207 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ argument
208 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
537 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr,
540 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr,
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_phy.c3059 u32 phy_addr = 0; in e1000_determine_phy_address() local
3065 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { in e1000_determine_phy_address()
3066 hw->phy.addr = phy_addr; in e1000_determine_phy_address()
3095 u32 phy_addr = 2; in e1000_get_phy_addr_for_bm_page() local
3098 phy_addr = 1; in e1000_get_phy_addr_for_bm_page()
3100 return phy_addr; in e1000_get_phy_addr_for_bm_page()
3538 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); in __e1000_read_phy_reg_hv() local
3569 hw->phy.addr = phy_addr; in __e1000_read_phy_reg_hv()
3647 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); in __e1000_write_phy_reg_hv() local
3694 hw->phy.addr = phy_addr; in __e1000_write_phy_reg_hv()
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/illumos-gate/usr/src/uts/common/io/i40e/core/
H A Di40e_prototype.h618 u16 reg, u8 phy_addr, u16 *value);
620 u16 reg, u8 phy_addr, u16 value);
622 u8 page, u16 reg, u8 phy_addr, u16 *value);
624 u8 page, u16 reg, u8 phy_addr, u16 value);
626 u8 page, u16 reg, u8 phy_addr, u16 *value);
628 u8 page, u16 reg, u8 phy_addr, u16 value);
H A Di40e_common.c6425 u16 reg, u8 phy_addr, u16 *value) in i40e_read_phy_register_clause22() argument
6433 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_read_phy_register_clause22()
6470 u16 reg, u8 phy_addr, u16 value) in i40e_write_phy_register_clause22() argument
6481 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_write_phy_register_clause22()
6511 u8 page, u16 reg, u8 phy_addr, u16 *value) in i40e_read_phy_register_clause45() argument
6520 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_read_phy_register_clause45()
6543 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_read_phy_register_clause45()
6585 u8 page, u16 reg, u8 phy_addr, u16 value) in i40e_write_phy_register_clause45() argument
6594 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_write_phy_register_clause45()
6619 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_write_phy_register_clause45()
[all …]
/illumos-gate/usr/src/uts/common/io/mii/
H A Dmiipriv.h50 uint8_t phy_addr; member
H A Dmii.c285 mh->m_bogus_phy.phy_addr = 0xff; in mii_alloc_instance()
950 *val = ph->phy_addr; in mii_m_getstat()
1071 return ((*mh->m_ops.mii_read)(mh->m_private, ph->phy_addr, reg)); in phy_read()
1079 (*mh->m_ops.mii_write)(mh->m_private, ph->phy_addr, reg, val); in phy_write()
1841 ph->phy_addr = curr_addr; in _mii_probe()
/illumos-gate/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_main.h246 uint64_t phy_addr; member
/illumos-gate/usr/src/cmd/bhyve/common/
H A Dpci_e82545.c408 uint8_t phy_addr, uint32_t data) in e82545_write_mdi() argument
410 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data); in e82545_write_mdi()
415 uint8_t phy_addr) in e82545_read_mdi() argument
434 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr); in e82545_read_mdi()
1835 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> in e82545_write_register() local
1846 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); in e82545_write_register()
1849 e82545_write_mdi(sc, reg_addr, phy_addr, in e82545_write_register()

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