1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "e1000_api.h"
36
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
50
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 124};
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
63
64 /**
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
67 *
68 * Setups up the function pointers to no-op functions
69 **/
e1000_init_phy_ops_generic(struct e1000_hw * hw)70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
74
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101 }
102
103 /**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 **/
e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG * hw,u16 E1000_UNUSEDARG data)107 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
108 u16 E1000_UNUSEDARG data)
109 {
110 DEBUGFUNC("e1000_null_set_page");
111 return E1000_SUCCESS;
112 }
113
114 /**
115 * e1000_null_read_reg - No-op function, return 0
116 * @hw: pointer to the HW structure
117 **/
e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG * data)118 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
119 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
120 {
121 DEBUGFUNC("e1000_null_read_reg");
122 return E1000_SUCCESS;
123 }
124
125 /**
126 * e1000_null_phy_generic - No-op function, return void
127 * @hw: pointer to the HW structure
128 **/
e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG * hw)129 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
130 {
131 DEBUGFUNC("e1000_null_phy_generic");
132 return;
133 }
134
135 /**
136 * e1000_null_lplu_state - No-op function, return 0
137 * @hw: pointer to the HW structure
138 **/
e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG * hw,bool E1000_UNUSEDARG active)139 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
140 bool E1000_UNUSEDARG active)
141 {
142 DEBUGFUNC("e1000_null_lplu_state");
143 return E1000_SUCCESS;
144 }
145
146 /**
147 * e1000_null_write_reg - No-op function, return 0
148 * @hw: pointer to the HW structure
149 **/
e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG data)150 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
151 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
152 {
153 DEBUGFUNC("e1000_null_write_reg");
154 return E1000_SUCCESS;
155 }
156
157 /**
158 * e1000_read_i2c_byte_null - No-op function, return 0
159 * @hw: pointer to hardware structure
160 * @byte_offset: byte offset to write
161 * @dev_addr: device address
162 * @data: data value read
163 *
164 **/
e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG * data)165 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
166 u8 E1000_UNUSEDARG byte_offset,
167 u8 E1000_UNUSEDARG dev_addr,
168 u8 E1000_UNUSEDARG *data)
169 {
170 DEBUGFUNC("e1000_read_i2c_byte_null");
171 return E1000_SUCCESS;
172 }
173
174 /**
175 * e1000_write_i2c_byte_null - No-op function, return 0
176 * @hw: pointer to hardware structure
177 * @byte_offset: byte offset to write
178 * @dev_addr: device address
179 * @data: data value to write
180 *
181 **/
e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG data)182 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
183 u8 E1000_UNUSEDARG byte_offset,
184 u8 E1000_UNUSEDARG dev_addr,
185 u8 E1000_UNUSEDARG data)
186 {
187 DEBUGFUNC("e1000_write_i2c_byte_null");
188 return E1000_SUCCESS;
189 }
190
191 /**
192 * e1000_check_reset_block_generic - Check if PHY reset is blocked
193 * @hw: pointer to the HW structure
194 *
195 * Read the PHY management control register and check whether a PHY reset
196 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
197 * return E1000_BLK_PHY_RESET (12).
198 **/
e1000_check_reset_block_generic(struct e1000_hw * hw)199 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
200 {
201 u32 manc;
202
203 DEBUGFUNC("e1000_check_reset_block");
204
205 manc = E1000_READ_REG(hw, E1000_MANC);
206
207 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
208 E1000_BLK_PHY_RESET : E1000_SUCCESS;
209 }
210
211 /**
212 * e1000_get_phy_id - Retrieve the PHY ID and revision
213 * @hw: pointer to the HW structure
214 *
215 * Reads the PHY registers and stores the PHY ID and possibly the PHY
216 * revision in the hardware structure.
217 **/
e1000_get_phy_id(struct e1000_hw * hw)218 s32 e1000_get_phy_id(struct e1000_hw *hw)
219 {
220 struct e1000_phy_info *phy = &hw->phy;
221 s32 ret_val = E1000_SUCCESS;
222 u16 phy_id;
223 u16 retry_count = 0;
224
225 DEBUGFUNC("e1000_get_phy_id");
226
227 if (!phy->ops.read_reg)
228 return E1000_SUCCESS;
229
230 while (retry_count < 2) {
231 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
232 if (ret_val)
233 return ret_val;
234
235 phy->id = (u32)(phy_id << 16);
236 usec_delay(20);
237 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
238 if (ret_val)
239 return ret_val;
240
241 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
242 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
243
244 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
245 return E1000_SUCCESS;
246
247 retry_count++;
248 }
249
250 return E1000_SUCCESS;
251 }
252
253 /**
254 * e1000_phy_reset_dsp_generic - Reset PHY DSP
255 * @hw: pointer to the HW structure
256 *
257 * Reset the digital signal processor.
258 **/
e1000_phy_reset_dsp_generic(struct e1000_hw * hw)259 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
260 {
261 s32 ret_val;
262
263 DEBUGFUNC("e1000_phy_reset_dsp_generic");
264
265 if (!hw->phy.ops.write_reg)
266 return E1000_SUCCESS;
267
268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
269 if (ret_val)
270 return ret_val;
271
272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
273 }
274
275 /**
276 * e1000_read_phy_reg_mdic - Read MDI control register
277 * @hw: pointer to the HW structure
278 * @offset: register offset to be read
279 * @data: pointer to the read data
280 *
281 * Reads the MDI control register in the PHY at offset and stores the
282 * information read to data.
283 **/
e1000_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)284 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
285 {
286 struct e1000_phy_info *phy = &hw->phy;
287 u32 i, mdic = 0;
288
289 DEBUGFUNC("e1000_read_phy_reg_mdic");
290
291 if (offset > MAX_PHY_REG_ADDRESS) {
292 DEBUGOUT1("PHY Address %d is out of range\n", offset);
293 return -E1000_ERR_PARAM;
294 }
295
296 /* Set up Op-code, Phy Address, and register offset in the MDI
297 * Control register. The MAC will take care of interfacing with the
298 * PHY to retrieve the desired data.
299 */
300 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
301 (phy->addr << E1000_MDIC_PHY_SHIFT) |
302 (E1000_MDIC_OP_READ));
303
304 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
305
306 /* Poll the ready bit to see if the MDI read completed
307 * Increasing the time out as testing showed failures with
308 * the lower time out
309 */
310 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
311 usec_delay_irq(50);
312 mdic = E1000_READ_REG(hw, E1000_MDIC);
313 if (mdic & E1000_MDIC_READY)
314 break;
315 }
316 if (!(mdic & E1000_MDIC_READY)) {
317 DEBUGOUT("MDI Read did not complete\n");
318 return -E1000_ERR_PHY;
319 }
320 if (mdic & E1000_MDIC_ERROR) {
321 DEBUGOUT("MDI Error\n");
322 return -E1000_ERR_PHY;
323 }
324 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
325 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
326 offset,
327 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
328 return -E1000_ERR_PHY;
329 }
330 *data = (u16) mdic;
331
332 /* Allow some time after each MDIC transaction to avoid
333 * reading duplicate data in the next MDIC transaction.
334 */
335 if (hw->mac.type == e1000_pch2lan)
336 usec_delay_irq(100);
337
338 return E1000_SUCCESS;
339 }
340
341 /**
342 * e1000_write_phy_reg_mdic - Write MDI control register
343 * @hw: pointer to the HW structure
344 * @offset: register offset to write to
345 * @data: data to write to register at offset
346 *
347 * Writes data to MDI control register in the PHY at offset.
348 **/
e1000_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)349 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
350 {
351 struct e1000_phy_info *phy = &hw->phy;
352 u32 i, mdic = 0;
353
354 DEBUGFUNC("e1000_write_phy_reg_mdic");
355
356 if (offset > MAX_PHY_REG_ADDRESS) {
357 DEBUGOUT1("PHY Address %d is out of range\n", offset);
358 return -E1000_ERR_PARAM;
359 }
360
361 /* Set up Op-code, Phy Address, and register offset in the MDI
362 * Control register. The MAC will take care of interfacing with the
363 * PHY to retrieve the desired data.
364 */
365 mdic = (((u32)data) |
366 (offset << E1000_MDIC_REG_SHIFT) |
367 (phy->addr << E1000_MDIC_PHY_SHIFT) |
368 (E1000_MDIC_OP_WRITE));
369
370 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
371
372 /* Poll the ready bit to see if the MDI read completed
373 * Increasing the time out as testing showed failures with
374 * the lower time out
375 */
376 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
377 usec_delay_irq(50);
378 mdic = E1000_READ_REG(hw, E1000_MDIC);
379 if (mdic & E1000_MDIC_READY)
380 break;
381 }
382 if (!(mdic & E1000_MDIC_READY)) {
383 DEBUGOUT("MDI Write did not complete\n");
384 return -E1000_ERR_PHY;
385 }
386 if (mdic & E1000_MDIC_ERROR) {
387 DEBUGOUT("MDI Error\n");
388 return -E1000_ERR_PHY;
389 }
390 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
391 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
392 offset,
393 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
394 return -E1000_ERR_PHY;
395 }
396
397 /* Allow some time after each MDIC transaction to avoid
398 * reading duplicate data in the next MDIC transaction.
399 */
400 if (hw->mac.type == e1000_pch2lan)
401 usec_delay_irq(100);
402
403 return E1000_SUCCESS;
404 }
405
406 /**
407 * e1000_read_phy_reg_i2c - Read PHY register using i2c
408 * @hw: pointer to the HW structure
409 * @offset: register offset to be read
410 * @data: pointer to the read data
411 *
412 * Reads the PHY register at offset using the i2c interface and stores the
413 * retrieved information in data.
414 **/
e1000_read_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 * data)415 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
416 {
417 struct e1000_phy_info *phy = &hw->phy;
418 u32 i, i2ccmd = 0;
419
420 DEBUGFUNC("e1000_read_phy_reg_i2c");
421
422 /* Set up Op-code, Phy Address, and register address in the I2CCMD
423 * register. The MAC will take care of interfacing with the
424 * PHY to retrieve the desired data.
425 */
426 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
427 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
428 (E1000_I2CCMD_OPCODE_READ));
429
430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
431
432 /* Poll the ready bit to see if the I2C read completed */
433 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
434 usec_delay(50);
435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
436 if (i2ccmd & E1000_I2CCMD_READY)
437 break;
438 }
439 if (!(i2ccmd & E1000_I2CCMD_READY)) {
440 DEBUGOUT("I2CCMD Read did not complete\n");
441 return -E1000_ERR_PHY;
442 }
443 if (i2ccmd & E1000_I2CCMD_ERROR) {
444 DEBUGOUT("I2CCMD Error bit set\n");
445 return -E1000_ERR_PHY;
446 }
447
448 /* Need to byte-swap the 16-bit value. */
449 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
450
451 return E1000_SUCCESS;
452 }
453
454 /**
455 * e1000_write_phy_reg_i2c - Write PHY register using i2c
456 * @hw: pointer to the HW structure
457 * @offset: register offset to write to
458 * @data: data to write at register offset
459 *
460 * Writes the data to PHY register at the offset using the i2c interface.
461 **/
e1000_write_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 data)462 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
463 {
464 struct e1000_phy_info *phy = &hw->phy;
465 u32 i, i2ccmd = 0;
466 u16 phy_data_swapped;
467
468 DEBUGFUNC("e1000_write_phy_reg_i2c");
469
470 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
471 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
472 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
473 hw->phy.addr);
474 return -E1000_ERR_CONFIG;
475 }
476
477 /* Swap the data bytes for the I2C interface */
478 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
479
480 /* Set up Op-code, Phy Address, and register address in the I2CCMD
481 * register. The MAC will take care of interfacing with the
482 * PHY to retrieve the desired data.
483 */
484 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
485 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
486 E1000_I2CCMD_OPCODE_WRITE |
487 phy_data_swapped);
488
489 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
490
491 /* Poll the ready bit to see if the I2C read completed */
492 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
493 usec_delay(50);
494 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
495 if (i2ccmd & E1000_I2CCMD_READY)
496 break;
497 }
498 if (!(i2ccmd & E1000_I2CCMD_READY)) {
499 DEBUGOUT("I2CCMD Write did not complete\n");
500 return -E1000_ERR_PHY;
501 }
502 if (i2ccmd & E1000_I2CCMD_ERROR) {
503 DEBUGOUT("I2CCMD Error bit set\n");
504 return -E1000_ERR_PHY;
505 }
506
507 return E1000_SUCCESS;
508 }
509
510 /**
511 * e1000_read_sfp_data_byte - Reads SFP module data.
512 * @hw: pointer to the HW structure
513 * @offset: byte location offset to be read
514 * @data: read data buffer pointer
515 *
516 * Reads one byte from SFP module data stored
517 * in SFP resided EEPROM memory or SFP diagnostic area.
518 * Function should be called with
519 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
520 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
521 * access
522 **/
e1000_read_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 * data)523 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
524 {
525 u32 i = 0;
526 u32 i2ccmd = 0;
527 u32 data_local = 0;
528
529 DEBUGFUNC("e1000_read_sfp_data_byte");
530
531 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
532 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
533 return -E1000_ERR_PHY;
534 }
535
536 /* Set up Op-code, EEPROM Address,in the I2CCMD
537 * register. The MAC will take care of interfacing with the
538 * EEPROM to retrieve the desired data.
539 */
540 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
541 E1000_I2CCMD_OPCODE_READ);
542
543 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
544
545 /* Poll the ready bit to see if the I2C read completed */
546 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
547 usec_delay(50);
548 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
549 if (data_local & E1000_I2CCMD_READY)
550 break;
551 }
552 if (!(data_local & E1000_I2CCMD_READY)) {
553 DEBUGOUT("I2CCMD Read did not complete\n");
554 return -E1000_ERR_PHY;
555 }
556 if (data_local & E1000_I2CCMD_ERROR) {
557 DEBUGOUT("I2CCMD Error bit set\n");
558 return -E1000_ERR_PHY;
559 }
560 *data = (u8) data_local & 0xFF;
561
562 return E1000_SUCCESS;
563 }
564
565 /**
566 * e1000_write_sfp_data_byte - Writes SFP module data.
567 * @hw: pointer to the HW structure
568 * @offset: byte location offset to write to
569 * @data: data to write
570 *
571 * Writes one byte to SFP module data stored
572 * in SFP resided EEPROM memory or SFP diagnostic area.
573 * Function should be called with
574 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
575 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
576 * access
577 **/
e1000_write_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 data)578 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
579 {
580 u32 i = 0;
581 u32 i2ccmd = 0;
582 u32 data_local = 0;
583
584 DEBUGFUNC("e1000_write_sfp_data_byte");
585
586 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
587 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
588 return -E1000_ERR_PHY;
589 }
590 /* The programming interface is 16 bits wide
591 * so we need to read the whole word first
592 * then update appropriate byte lane and write
593 * the updated word back.
594 */
595 /* Set up Op-code, EEPROM Address,in the I2CCMD
596 * register. The MAC will take care of interfacing
597 * with an EEPROM to write the data given.
598 */
599 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
600 E1000_I2CCMD_OPCODE_READ);
601 /* Set a command to read single word */
602 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
603 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
604 usec_delay(50);
605 /* Poll the ready bit to see if lastly
606 * launched I2C operation completed
607 */
608 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
609 if (i2ccmd & E1000_I2CCMD_READY) {
610 /* Check if this is READ or WRITE phase */
611 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
612 E1000_I2CCMD_OPCODE_READ) {
613 /* Write the selected byte
614 * lane and update whole word
615 */
616 data_local = i2ccmd & 0xFF00;
617 data_local |= data;
618 i2ccmd = ((offset <<
619 E1000_I2CCMD_REG_ADDR_SHIFT) |
620 E1000_I2CCMD_OPCODE_WRITE | data_local);
621 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
622 } else {
623 break;
624 }
625 }
626 }
627 if (!(i2ccmd & E1000_I2CCMD_READY)) {
628 DEBUGOUT("I2CCMD Write did not complete\n");
629 return -E1000_ERR_PHY;
630 }
631 if (i2ccmd & E1000_I2CCMD_ERROR) {
632 DEBUGOUT("I2CCMD Error bit set\n");
633 return -E1000_ERR_PHY;
634 }
635 return E1000_SUCCESS;
636 }
637
638 /**
639 * e1000_read_phy_reg_m88 - Read m88 PHY register
640 * @hw: pointer to the HW structure
641 * @offset: register offset to be read
642 * @data: pointer to the read data
643 *
644 * Acquires semaphore, if necessary, then reads the PHY register at offset
645 * and storing the retrieved information in data. Release any acquired
646 * semaphores before exiting.
647 **/
e1000_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)648 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
649 {
650 s32 ret_val;
651
652 DEBUGFUNC("e1000_read_phy_reg_m88");
653
654 if (!hw->phy.ops.acquire)
655 return E1000_SUCCESS;
656
657 ret_val = hw->phy.ops.acquire(hw);
658 if (ret_val)
659 return ret_val;
660
661 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
662 data);
663
664 hw->phy.ops.release(hw);
665
666 return ret_val;
667 }
668
669 /**
670 * e1000_write_phy_reg_m88 - Write m88 PHY register
671 * @hw: pointer to the HW structure
672 * @offset: register offset to write to
673 * @data: data to write at register offset
674 *
675 * Acquires semaphore, if necessary, then writes the data to PHY register
676 * at the offset. Release any acquired semaphores before exiting.
677 **/
e1000_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)678 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
679 {
680 s32 ret_val;
681
682 DEBUGFUNC("e1000_write_phy_reg_m88");
683
684 if (!hw->phy.ops.acquire)
685 return E1000_SUCCESS;
686
687 ret_val = hw->phy.ops.acquire(hw);
688 if (ret_val)
689 return ret_val;
690
691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
692 data);
693
694 hw->phy.ops.release(hw);
695
696 return ret_val;
697 }
698
699 /**
700 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
701 * @hw: pointer to the HW structure
702 * @page: page to set (shifted left when necessary)
703 *
704 * Sets PHY page required for PHY register access. Assumes semaphore is
705 * already acquired. Note, this function sets phy.addr to 1 so the caller
706 * must set it appropriately (if necessary) after this function returns.
707 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)708 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
709 {
710 DEBUGFUNC("e1000_set_page_igp");
711
712 DEBUGOUT1("Setting page 0x%x\n", page);
713
714 hw->phy.addr = 1;
715
716 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
717 }
718
719 /**
720 * __e1000_read_phy_reg_igp - Read igp PHY register
721 * @hw: pointer to the HW structure
722 * @offset: register offset to be read
723 * @data: pointer to the read data
724 * @locked: semaphore has already been acquired or not
725 *
726 * Acquires semaphore, if necessary, then reads the PHY register at offset
727 * and stores the retrieved information in data. Release any acquired
728 * semaphores before exiting.
729 **/
__e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)730 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
731 bool locked)
732 {
733 s32 ret_val = E1000_SUCCESS;
734
735 DEBUGFUNC("__e1000_read_phy_reg_igp");
736
737 if (!locked) {
738 if (!hw->phy.ops.acquire)
739 return E1000_SUCCESS;
740
741 ret_val = hw->phy.ops.acquire(hw);
742 if (ret_val)
743 return ret_val;
744 }
745
746 if (offset > MAX_PHY_MULTI_PAGE_REG)
747 ret_val = e1000_write_phy_reg_mdic(hw,
748 IGP01E1000_PHY_PAGE_SELECT,
749 (u16)offset);
750 if (!ret_val)
751 ret_val = e1000_read_phy_reg_mdic(hw,
752 MAX_PHY_REG_ADDRESS & offset,
753 data);
754 if (!locked)
755 hw->phy.ops.release(hw);
756
757 return ret_val;
758 }
759
760 /**
761 * e1000_read_phy_reg_igp - Read igp PHY register
762 * @hw: pointer to the HW structure
763 * @offset: register offset to be read
764 * @data: pointer to the read data
765 *
766 * Acquires semaphore then reads the PHY register at offset and stores the
767 * retrieved information in data.
768 * Release the acquired semaphore before exiting.
769 **/
e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)770 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
771 {
772 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
773 }
774
775 /**
776 * e1000_read_phy_reg_igp_locked - Read igp PHY register
777 * @hw: pointer to the HW structure
778 * @offset: register offset to be read
779 * @data: pointer to the read data
780 *
781 * Reads the PHY register at offset and stores the retrieved information
782 * in data. Assumes semaphore already acquired.
783 **/
e1000_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)784 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
785 {
786 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
787 }
788
789 /**
790 * e1000_write_phy_reg_igp - Write igp PHY register
791 * @hw: pointer to the HW structure
792 * @offset: register offset to write to
793 * @data: data to write at register offset
794 * @locked: semaphore has already been acquired or not
795 *
796 * Acquires semaphore, if necessary, then writes the data to PHY register
797 * at the offset. Release any acquired semaphores before exiting.
798 **/
__e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)799 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
800 bool locked)
801 {
802 s32 ret_val = E1000_SUCCESS;
803
804 DEBUGFUNC("e1000_write_phy_reg_igp");
805
806 if (!locked) {
807 if (!hw->phy.ops.acquire)
808 return E1000_SUCCESS;
809
810 ret_val = hw->phy.ops.acquire(hw);
811 if (ret_val)
812 return ret_val;
813 }
814
815 if (offset > MAX_PHY_MULTI_PAGE_REG)
816 ret_val = e1000_write_phy_reg_mdic(hw,
817 IGP01E1000_PHY_PAGE_SELECT,
818 (u16)offset);
819 if (!ret_val)
820 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
821 offset,
822 data);
823 if (!locked)
824 hw->phy.ops.release(hw);
825
826 return ret_val;
827 }
828
829 /**
830 * e1000_write_phy_reg_igp - Write igp PHY register
831 * @hw: pointer to the HW structure
832 * @offset: register offset to write to
833 * @data: data to write at register offset
834 *
835 * Acquires semaphore then writes the data to PHY register
836 * at the offset. Release any acquired semaphores before exiting.
837 **/
e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)838 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
839 {
840 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
841 }
842
843 /**
844 * e1000_write_phy_reg_igp_locked - Write igp PHY register
845 * @hw: pointer to the HW structure
846 * @offset: register offset to write to
847 * @data: data to write at register offset
848 *
849 * Writes the data to PHY register at the offset.
850 * Assumes semaphore already acquired.
851 **/
e1000_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)852 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
853 {
854 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
855 }
856
857 /**
858 * __e1000_read_kmrn_reg - Read kumeran register
859 * @hw: pointer to the HW structure
860 * @offset: register offset to be read
861 * @data: pointer to the read data
862 * @locked: semaphore has already been acquired or not
863 *
864 * Acquires semaphore, if necessary. Then reads the PHY register at offset
865 * using the kumeran interface. The information retrieved is stored in data.
866 * Release any acquired semaphores before exiting.
867 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)868 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
869 bool locked)
870 {
871 u32 kmrnctrlsta;
872
873 DEBUGFUNC("__e1000_read_kmrn_reg");
874
875 if (!locked) {
876 s32 ret_val = E1000_SUCCESS;
877
878 if (!hw->phy.ops.acquire)
879 return E1000_SUCCESS;
880
881 ret_val = hw->phy.ops.acquire(hw);
882 if (ret_val)
883 return ret_val;
884 }
885
886 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
887 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
888 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
889 E1000_WRITE_FLUSH(hw);
890
891 usec_delay(2);
892
893 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
894 *data = (u16)kmrnctrlsta;
895
896 if (!locked)
897 hw->phy.ops.release(hw);
898
899 return E1000_SUCCESS;
900 }
901
902 /**
903 * e1000_read_kmrn_reg_generic - Read kumeran register
904 * @hw: pointer to the HW structure
905 * @offset: register offset to be read
906 * @data: pointer to the read data
907 *
908 * Acquires semaphore then reads the PHY register at offset using the
909 * kumeran interface. The information retrieved is stored in data.
910 * Release the acquired semaphore before exiting.
911 **/
e1000_read_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 * data)912 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
913 {
914 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
915 }
916
917 /**
918 * e1000_read_kmrn_reg_locked - Read kumeran register
919 * @hw: pointer to the HW structure
920 * @offset: register offset to be read
921 * @data: pointer to the read data
922 *
923 * Reads the PHY register at offset using the kumeran interface. The
924 * information retrieved is stored in data.
925 * Assumes semaphore already acquired.
926 **/
e1000_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)927 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
928 {
929 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
930 }
931
932 /**
933 * __e1000_write_kmrn_reg - Write kumeran register
934 * @hw: pointer to the HW structure
935 * @offset: register offset to write to
936 * @data: data to write at register offset
937 * @locked: semaphore has already been acquired or not
938 *
939 * Acquires semaphore, if necessary. Then write the data to PHY register
940 * at the offset using the kumeran interface. Release any acquired semaphores
941 * before exiting.
942 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)943 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
944 bool locked)
945 {
946 u32 kmrnctrlsta;
947
948 DEBUGFUNC("e1000_write_kmrn_reg_generic");
949
950 if (!locked) {
951 s32 ret_val = E1000_SUCCESS;
952
953 if (!hw->phy.ops.acquire)
954 return E1000_SUCCESS;
955
956 ret_val = hw->phy.ops.acquire(hw);
957 if (ret_val)
958 return ret_val;
959 }
960
961 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
962 E1000_KMRNCTRLSTA_OFFSET) | data;
963 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
964 E1000_WRITE_FLUSH(hw);
965
966 usec_delay(2);
967
968 if (!locked)
969 hw->phy.ops.release(hw);
970
971 return E1000_SUCCESS;
972 }
973
974 /**
975 * e1000_write_kmrn_reg_generic - Write kumeran register
976 * @hw: pointer to the HW structure
977 * @offset: register offset to write to
978 * @data: data to write at register offset
979 *
980 * Acquires semaphore then writes the data to the PHY register at the offset
981 * using the kumeran interface. Release the acquired semaphore before exiting.
982 **/
e1000_write_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 data)983 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
984 {
985 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
986 }
987
988 /**
989 * e1000_write_kmrn_reg_locked - Write kumeran register
990 * @hw: pointer to the HW structure
991 * @offset: register offset to write to
992 * @data: data to write at register offset
993 *
994 * Write the data to PHY register at the offset using the kumeran interface.
995 * Assumes semaphore already acquired.
996 **/
e1000_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)997 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
998 {
999 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
1000 }
1001
1002 /**
1003 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1004 * @hw: pointer to the HW structure
1005 *
1006 * Sets up Master/slave mode
1007 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)1008 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1009 {
1010 s32 ret_val;
1011 u16 phy_data;
1012
1013 /* Resolve Master/Slave mode */
1014 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* load defaults for future use */
1019 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1020 ((phy_data & CR_1000T_MS_VALUE) ?
1021 e1000_ms_force_master :
1022 e1000_ms_force_slave) : e1000_ms_auto;
1023
1024 switch (hw->phy.ms_type) {
1025 case e1000_ms_force_master:
1026 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1027 break;
1028 case e1000_ms_force_slave:
1029 phy_data |= CR_1000T_MS_ENABLE;
1030 phy_data &= ~(CR_1000T_MS_VALUE);
1031 break;
1032 case e1000_ms_auto:
1033 phy_data &= ~CR_1000T_MS_ENABLE;
1034 /* fall-through */
1035 default:
1036 break;
1037 }
1038
1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1040 }
1041
1042 /**
1043 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1044 * @hw: pointer to the HW structure
1045 *
1046 * Sets up Carrier-sense on Transmit and downshift values.
1047 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)1048 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1049 {
1050 s32 ret_val;
1051 u16 phy_data;
1052
1053 DEBUGFUNC("e1000_copper_link_setup_82577");
1054
1055 if (hw->phy.type == e1000_phy_82580) {
1056 ret_val = hw->phy.ops.reset(hw);
1057 if (ret_val) {
1058 DEBUGOUT("Error resetting the PHY.\n");
1059 return ret_val;
1060 }
1061 }
1062
1063 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1064 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1065 if (ret_val)
1066 return ret_val;
1067
1068 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1069
1070 /* Enable downshift */
1071 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1072
1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1074 if (ret_val)
1075 return ret_val;
1076
1077 /* Set MDI/MDIX mode */
1078 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1079 if (ret_val)
1080 return ret_val;
1081 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1082 /* Options:
1083 * 0 - Auto (default)
1084 * 1 - MDI mode
1085 * 2 - MDI-X mode
1086 */
1087 switch (hw->phy.mdix) {
1088 case 1:
1089 break;
1090 case 2:
1091 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1092 break;
1093 case 0:
1094 default:
1095 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1096 break;
1097 }
1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1099 if (ret_val)
1100 return ret_val;
1101
1102 return e1000_set_master_slave_mode(hw);
1103 }
1104
1105 /**
1106 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1107 * @hw: pointer to the HW structure
1108 *
1109 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1110 * and downshift values are set also.
1111 **/
e1000_copper_link_setup_m88(struct e1000_hw * hw)1112 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1113 {
1114 struct e1000_phy_info *phy = &hw->phy;
1115 s32 ret_val;
1116 u16 phy_data;
1117
1118 DEBUGFUNC("e1000_copper_link_setup_m88");
1119
1120
1121 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1122 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1123 if (ret_val)
1124 return ret_val;
1125
1126 /* For BM PHY this bit is downshift enable */
1127 if (phy->type != e1000_phy_bm)
1128 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1129
1130 /* Options:
1131 * MDI/MDI-X = 0 (default)
1132 * 0 - Auto for all speeds
1133 * 1 - MDI mode
1134 * 2 - MDI-X mode
1135 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1136 */
1137 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1138
1139 switch (phy->mdix) {
1140 case 1:
1141 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1142 break;
1143 case 2:
1144 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1145 break;
1146 case 3:
1147 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1148 break;
1149 case 0:
1150 default:
1151 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1152 break;
1153 }
1154
1155 /* Options:
1156 * disable_polarity_correction = 0 (default)
1157 * Automatic Correction for Reversed Cable Polarity
1158 * 0 - Disabled
1159 * 1 - Enabled
1160 */
1161 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1162 if (phy->disable_polarity_correction)
1163 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1164
1165 /* Enable downshift on BM (disabled by default) */
1166 if (phy->type == e1000_phy_bm) {
1167 /* For 82574/82583, first disable then enable downshift */
1168 if (phy->id == BME1000_E_PHY_ID_R2) {
1169 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1171 phy_data);
1172 if (ret_val)
1173 return ret_val;
1174 /* Commit the changes. */
1175 ret_val = phy->ops.commit(hw);
1176 if (ret_val) {
1177 DEBUGOUT("Error committing the PHY changes\n");
1178 return ret_val;
1179 }
1180 }
1181
1182 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1183 }
1184
1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1186 if (ret_val)
1187 return ret_val;
1188
1189 if ((phy->type == e1000_phy_m88) &&
1190 (phy->revision < E1000_REVISION_4) &&
1191 (phy->id != BME1000_E_PHY_ID_R2)) {
1192 /* Force TX_CLK in the Extended PHY Specific Control Register
1193 * to 25MHz clock.
1194 */
1195 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1196 &phy_data);
1197 if (ret_val)
1198 return ret_val;
1199
1200 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1201
1202 if ((phy->revision == E1000_REVISION_2) &&
1203 (phy->id == M88E1111_I_PHY_ID)) {
1204 /* 82573L PHY - set the downshift counter to 5x. */
1205 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1206 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1207 } else {
1208 /* Configure Master and Slave downshift values */
1209 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1210 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1211 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1212 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1213 }
1214 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1215 phy_data);
1216 if (ret_val)
1217 return ret_val;
1218 }
1219
1220 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1221 /* Set PHY page 0, register 29 to 0x0003 */
1222 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1223 if (ret_val)
1224 return ret_val;
1225
1226 /* Set PHY page 0, register 30 to 0x0000 */
1227 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1228 if (ret_val)
1229 return ret_val;
1230 }
1231
1232 /* Commit the changes. */
1233 ret_val = phy->ops.commit(hw);
1234 if (ret_val) {
1235 DEBUGOUT("Error committing the PHY changes\n");
1236 return ret_val;
1237 }
1238
1239 if (phy->type == e1000_phy_82578) {
1240 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1241 &phy_data);
1242 if (ret_val)
1243 return ret_val;
1244
1245 /* 82578 PHY - set the downshift count to 1x. */
1246 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1247 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1248 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1249 phy_data);
1250 if (ret_val)
1251 return ret_val;
1252 }
1253
1254 return E1000_SUCCESS;
1255 }
1256
1257 /**
1258 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1259 * @hw: pointer to the HW structure
1260 *
1261 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1262 * Also enables and sets the downshift parameters.
1263 **/
e1000_copper_link_setup_m88_gen2(struct e1000_hw * hw)1264 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1265 {
1266 struct e1000_phy_info *phy = &hw->phy;
1267 s32 ret_val;
1268 u16 phy_data;
1269
1270 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1271
1272
1273 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1274 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1275 if (ret_val)
1276 return ret_val;
1277
1278 /* Options:
1279 * MDI/MDI-X = 0 (default)
1280 * 0 - Auto for all speeds
1281 * 1 - MDI mode
1282 * 2 - MDI-X mode
1283 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1284 */
1285 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1286
1287 switch (phy->mdix) {
1288 case 1:
1289 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1290 break;
1291 case 2:
1292 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1293 break;
1294 case 3:
1295 /* M88E1112 does not support this mode) */
1296 if (phy->id != M88E1112_E_PHY_ID) {
1297 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1298 break;
1299 }
1300 /* FALLTHROUGH */
1301 case 0:
1302 default:
1303 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1304 break;
1305 }
1306
1307 /* Options:
1308 * disable_polarity_correction = 0 (default)
1309 * Automatic Correction for Reversed Cable Polarity
1310 * 0 - Disabled
1311 * 1 - Enabled
1312 */
1313 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1314 if (phy->disable_polarity_correction)
1315 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1316
1317 /* Enable downshift and setting it to X6 */
1318 if (phy->id == M88E1543_E_PHY_ID) {
1319 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1320 ret_val =
1321 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1322 if (ret_val)
1323 return ret_val;
1324
1325 ret_val = phy->ops.commit(hw);
1326 if (ret_val) {
1327 DEBUGOUT("Error committing the PHY changes\n");
1328 return ret_val;
1329 }
1330 }
1331
1332 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1333 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1334 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1335
1336 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1337 if (ret_val)
1338 return ret_val;
1339
1340 /* Commit the changes. */
1341 ret_val = phy->ops.commit(hw);
1342 if (ret_val) {
1343 DEBUGOUT("Error committing the PHY changes\n");
1344 return ret_val;
1345 }
1346
1347 ret_val = e1000_set_master_slave_mode(hw);
1348 if (ret_val)
1349 return ret_val;
1350
1351 return E1000_SUCCESS;
1352 }
1353
1354 /**
1355 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1356 * @hw: pointer to the HW structure
1357 *
1358 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1359 * igp PHY's.
1360 **/
e1000_copper_link_setup_igp(struct e1000_hw * hw)1361 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1362 {
1363 struct e1000_phy_info *phy = &hw->phy;
1364 s32 ret_val;
1365 u16 data;
1366
1367 DEBUGFUNC("e1000_copper_link_setup_igp");
1368
1369
1370 ret_val = hw->phy.ops.reset(hw);
1371 if (ret_val) {
1372 DEBUGOUT("Error resetting the PHY.\n");
1373 return ret_val;
1374 }
1375
1376 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1377 * timeout issues when LFS is enabled.
1378 */
1379 msec_delay(100);
1380
1381 /* The NVM settings will configure LPLU in D3 for
1382 * non-IGP1 PHYs.
1383 */
1384 if (phy->type == e1000_phy_igp) {
1385 /* disable lplu d3 during driver init */
1386 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1387 if (ret_val) {
1388 DEBUGOUT("Error Disabling LPLU D3\n");
1389 return ret_val;
1390 }
1391 }
1392
1393 /* disable lplu d0 during driver init */
1394 if (hw->phy.ops.set_d0_lplu_state) {
1395 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1396 if (ret_val) {
1397 DEBUGOUT("Error Disabling LPLU D0\n");
1398 return ret_val;
1399 }
1400 }
1401 /* Configure mdi-mdix settings */
1402 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1403 if (ret_val)
1404 return ret_val;
1405
1406 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1407
1408 switch (phy->mdix) {
1409 case 1:
1410 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1411 break;
1412 case 2:
1413 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1414 break;
1415 case 0:
1416 default:
1417 data |= IGP01E1000_PSCR_AUTO_MDIX;
1418 break;
1419 }
1420 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1421 if (ret_val)
1422 return ret_val;
1423
1424 /* set auto-master slave resolution settings */
1425 if (hw->mac.autoneg) {
1426 /* when autonegotiation advertisement is only 1000Mbps then we
1427 * should disable SmartSpeed and enable Auto MasterSlave
1428 * resolution as hardware default.
1429 */
1430 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1431 /* Disable SmartSpeed */
1432 ret_val = phy->ops.read_reg(hw,
1433 IGP01E1000_PHY_PORT_CONFIG,
1434 &data);
1435 if (ret_val)
1436 return ret_val;
1437
1438 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1439 ret_val = phy->ops.write_reg(hw,
1440 IGP01E1000_PHY_PORT_CONFIG,
1441 data);
1442 if (ret_val)
1443 return ret_val;
1444
1445 /* Set auto Master/Slave resolution process */
1446 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1447 if (ret_val)
1448 return ret_val;
1449
1450 data &= ~CR_1000T_MS_ENABLE;
1451 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1452 if (ret_val)
1453 return ret_val;
1454 }
1455
1456 ret_val = e1000_set_master_slave_mode(hw);
1457 }
1458
1459 return ret_val;
1460 }
1461
1462 /**
1463 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1464 * @hw: pointer to the HW structure
1465 *
1466 * Reads the MII auto-neg advertisement register and/or the 1000T control
1467 * register and if the PHY is already setup for auto-negotiation, then
1468 * return successful. Otherwise, setup advertisement and flow control to
1469 * the appropriate values for the wanted auto-negotiation.
1470 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)1471 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1472 {
1473 struct e1000_phy_info *phy = &hw->phy;
1474 s32 ret_val;
1475 u16 mii_autoneg_adv_reg;
1476 u16 mii_1000t_ctrl_reg = 0;
1477
1478 DEBUGFUNC("e1000_phy_setup_autoneg");
1479
1480 phy->autoneg_advertised &= phy->autoneg_mask;
1481
1482 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1483 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1484 if (ret_val)
1485 return ret_val;
1486
1487 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1488 /* Read the MII 1000Base-T Control Register (Address 9). */
1489 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1490 &mii_1000t_ctrl_reg);
1491 if (ret_val)
1492 return ret_val;
1493 }
1494
1495 /* Need to parse both autoneg_advertised and fc and set up
1496 * the appropriate PHY registers. First we will parse for
1497 * autoneg_advertised software override. Since we can advertise
1498 * a plethora of combinations, we need to check each bit
1499 * individually.
1500 */
1501
1502 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1503 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1504 * the 1000Base-T Control Register (Address 9).
1505 */
1506 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1507 NWAY_AR_100TX_HD_CAPS |
1508 NWAY_AR_10T_FD_CAPS |
1509 NWAY_AR_10T_HD_CAPS);
1510 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1511
1512 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1513
1514 /* Do we want to advertise 10 Mb Half Duplex? */
1515 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1516 DEBUGOUT("Advertise 10mb Half duplex\n");
1517 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1518 }
1519
1520 /* Do we want to advertise 10 Mb Full Duplex? */
1521 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1522 DEBUGOUT("Advertise 10mb Full duplex\n");
1523 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1524 }
1525
1526 /* Do we want to advertise 100 Mb Half Duplex? */
1527 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1528 DEBUGOUT("Advertise 100mb Half duplex\n");
1529 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1530 }
1531
1532 /* Do we want to advertise 100 Mb Full Duplex? */
1533 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1534 DEBUGOUT("Advertise 100mb Full duplex\n");
1535 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1536 }
1537
1538 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1539 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1540 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1541
1542 /* Do we want to advertise 1000 Mb Full Duplex? */
1543 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1544 DEBUGOUT("Advertise 1000mb Full duplex\n");
1545 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1546 }
1547
1548 /* Check for a software override of the flow control settings, and
1549 * setup the PHY advertisement registers accordingly. If
1550 * auto-negotiation is enabled, then software will have to set the
1551 * "PAUSE" bits to the correct value in the Auto-Negotiation
1552 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1553 * negotiation.
1554 *
1555 * The possible values of the "fc" parameter are:
1556 * 0: Flow control is completely disabled
1557 * 1: Rx flow control is enabled (we can receive pause frames
1558 * but not send pause frames).
1559 * 2: Tx flow control is enabled (we can send pause frames
1560 * but we do not support receiving pause frames).
1561 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1562 * other: No software override. The flow control configuration
1563 * in the EEPROM is used.
1564 */
1565 switch (hw->fc.current_mode) {
1566 case e1000_fc_none:
1567 /* Flow control (Rx & Tx) is completely disabled by a
1568 * software over-ride.
1569 */
1570 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1571 break;
1572 case e1000_fc_rx_pause:
1573 /* Rx Flow control is enabled, and Tx Flow control is
1574 * disabled, by a software over-ride.
1575 *
1576 * Since there really isn't a way to advertise that we are
1577 * capable of Rx Pause ONLY, we will advertise that we
1578 * support both symmetric and asymmetric Rx PAUSE. Later
1579 * (in e1000_config_fc_after_link_up) we will disable the
1580 * hw's ability to send PAUSE frames.
1581 */
1582 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1583 break;
1584 case e1000_fc_tx_pause:
1585 /* Tx Flow control is enabled, and Rx Flow control is
1586 * disabled, by a software over-ride.
1587 */
1588 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1589 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1590 break;
1591 case e1000_fc_full:
1592 /* Flow control (both Rx and Tx) is enabled by a software
1593 * over-ride.
1594 */
1595 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1596 break;
1597 default:
1598 DEBUGOUT("Flow control param set incorrectly\n");
1599 return -E1000_ERR_CONFIG;
1600 }
1601
1602 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1603 if (ret_val)
1604 return ret_val;
1605
1606 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1607
1608 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1609 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1610 mii_1000t_ctrl_reg);
1611
1612 return ret_val;
1613 }
1614
1615 /**
1616 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1617 * @hw: pointer to the HW structure
1618 *
1619 * Performs initial bounds checking on autoneg advertisement parameter, then
1620 * configure to advertise the full capability. Setup the PHY to autoneg
1621 * and restart the negotiation process between the link partner. If
1622 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1623 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1624 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1625 {
1626 struct e1000_phy_info *phy = &hw->phy;
1627 s32 ret_val;
1628 u16 phy_ctrl;
1629
1630 DEBUGFUNC("e1000_copper_link_autoneg");
1631
1632 /* Perform some bounds checking on the autoneg advertisement
1633 * parameter.
1634 */
1635 phy->autoneg_advertised &= phy->autoneg_mask;
1636
1637 /* If autoneg_advertised is zero, we assume it was not defaulted
1638 * by the calling code so we set to advertise full capability.
1639 */
1640 if (!phy->autoneg_advertised)
1641 phy->autoneg_advertised = phy->autoneg_mask;
1642
1643 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1644 ret_val = e1000_phy_setup_autoneg(hw);
1645 if (ret_val) {
1646 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1647 return ret_val;
1648 }
1649 DEBUGOUT("Restarting Auto-Neg\n");
1650
1651 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1652 * the Auto Neg Restart bit in the PHY control register.
1653 */
1654 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1655 if (ret_val)
1656 return ret_val;
1657
1658 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1659 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1660 if (ret_val)
1661 return ret_val;
1662
1663 /* Does the user want to wait for Auto-Neg to complete here, or
1664 * check at a later time (for example, callback routine).
1665 */
1666 if (phy->autoneg_wait_to_complete) {
1667 ret_val = e1000_wait_autoneg(hw);
1668 if (ret_val) {
1669 DEBUGOUT("Error while waiting for autoneg to complete\n");
1670 return ret_val;
1671 }
1672 }
1673
1674 hw->mac.get_link_status = TRUE;
1675
1676 return ret_val;
1677 }
1678
1679 /**
1680 * e1000_setup_copper_link_generic - Configure copper link settings
1681 * @hw: pointer to the HW structure
1682 *
1683 * Calls the appropriate function to configure the link for auto-neg or forced
1684 * speed and duplex. Then we check for link, once link is established calls
1685 * to configure collision distance and flow control are called. If link is
1686 * not established, we return -E1000_ERR_PHY (-2).
1687 **/
e1000_setup_copper_link_generic(struct e1000_hw * hw)1688 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1689 {
1690 s32 ret_val;
1691 bool link;
1692
1693 DEBUGFUNC("e1000_setup_copper_link_generic");
1694
1695 if (hw->mac.autoneg) {
1696 /* Setup autoneg and flow control advertisement and perform
1697 * autonegotiation.
1698 */
1699 ret_val = e1000_copper_link_autoneg(hw);
1700 if (ret_val)
1701 return ret_val;
1702 } else {
1703 /* PHY will be set to 10H, 10F, 100H or 100F
1704 * depending on user settings.
1705 */
1706 DEBUGOUT("Forcing Speed and Duplex\n");
1707 ret_val = hw->phy.ops.force_speed_duplex(hw);
1708 if (ret_val) {
1709 DEBUGOUT("Error Forcing Speed and Duplex\n");
1710 return ret_val;
1711 }
1712 }
1713
1714 /* Check link status. Wait up to 100 microseconds for link to become
1715 * valid.
1716 */
1717 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1718 &link);
1719 if (ret_val)
1720 return ret_val;
1721
1722 if (link) {
1723 DEBUGOUT("Valid link established!!!\n");
1724 hw->mac.ops.config_collision_dist(hw);
1725 ret_val = e1000_config_fc_after_link_up_generic(hw);
1726 } else {
1727 DEBUGOUT("Unable to establish link!!!\n");
1728 }
1729
1730 return ret_val;
1731 }
1732
1733 /**
1734 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1735 * @hw: pointer to the HW structure
1736 *
1737 * Calls the PHY setup function to force speed and duplex. Clears the
1738 * auto-crossover to force MDI manually. Waits for link and returns
1739 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1740 **/
e1000_phy_force_speed_duplex_igp(struct e1000_hw * hw)1741 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1742 {
1743 struct e1000_phy_info *phy = &hw->phy;
1744 s32 ret_val;
1745 u16 phy_data;
1746 bool link;
1747
1748 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1749
1750 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1751 if (ret_val)
1752 return ret_val;
1753
1754 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1755
1756 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1757 if (ret_val)
1758 return ret_val;
1759
1760 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1761 * forced whenever speed and duplex are forced.
1762 */
1763 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1764 if (ret_val)
1765 return ret_val;
1766
1767 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1768 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1769
1770 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1771 if (ret_val)
1772 return ret_val;
1773
1774 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1775
1776 usec_delay(1);
1777
1778 if (phy->autoneg_wait_to_complete) {
1779 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1780
1781 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1782 100000, &link);
1783 if (ret_val)
1784 return ret_val;
1785
1786 if (!link)
1787 DEBUGOUT("Link taking longer than expected.\n");
1788
1789 /* Try once more */
1790 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1791 100000, &link);
1792 }
1793
1794 return ret_val;
1795 }
1796
1797 /**
1798 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1799 * @hw: pointer to the HW structure
1800 *
1801 * Calls the PHY setup function to force speed and duplex. Clears the
1802 * auto-crossover to force MDI manually. Resets the PHY to commit the
1803 * changes. If time expires while waiting for link up, we reset the DSP.
1804 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1805 * successful completion, else return corresponding error code.
1806 **/
e1000_phy_force_speed_duplex_m88(struct e1000_hw * hw)1807 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1808 {
1809 struct e1000_phy_info *phy = &hw->phy;
1810 s32 ret_val;
1811 u16 phy_data;
1812 bool link;
1813
1814 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1815
1816 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1817 if (phy->type != e1000_phy_i210) {
1818 /* Clear Auto-Crossover to force MDI manually. M88E1000
1819 * requires MDI forced whenever speed and duplex are forced.
1820 */
1821 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1822 &phy_data);
1823 if (ret_val)
1824 return ret_val;
1825
1826 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1827 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1828 phy_data);
1829 if (ret_val)
1830 return ret_val;
1831
1832 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1833 }
1834
1835 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1836 if (ret_val)
1837 return ret_val;
1838
1839 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1840
1841 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1842 if (ret_val)
1843 return ret_val;
1844
1845 /* Reset the phy to commit changes. */
1846 ret_val = hw->phy.ops.commit(hw);
1847 if (ret_val)
1848 return ret_val;
1849
1850 if (phy->autoneg_wait_to_complete) {
1851 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1852
1853 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1854 100000, &link);
1855 if (ret_val)
1856 return ret_val;
1857
1858 if (!link) {
1859 bool reset_dsp = TRUE;
1860
1861 switch (hw->phy.id) {
1862 case I347AT4_E_PHY_ID:
1863 case M88E1340M_E_PHY_ID:
1864 case M88E1112_E_PHY_ID:
1865 case M88E1543_E_PHY_ID:
1866 case M88E1512_E_PHY_ID:
1867 case I210_I_PHY_ID:
1868 reset_dsp = FALSE;
1869 break;
1870 default:
1871 if (hw->phy.type != e1000_phy_m88)
1872 reset_dsp = FALSE;
1873 break;
1874 }
1875
1876 if (!reset_dsp) {
1877 DEBUGOUT("Link taking longer than expected.\n");
1878 } else {
1879 /* We didn't get link.
1880 * Reset the DSP and cross our fingers.
1881 */
1882 ret_val = phy->ops.write_reg(hw,
1883 M88E1000_PHY_PAGE_SELECT,
1884 0x001d);
1885 if (ret_val)
1886 return ret_val;
1887 ret_val = e1000_phy_reset_dsp_generic(hw);
1888 if (ret_val)
1889 return ret_val;
1890 }
1891 }
1892
1893 /* Try once more */
1894 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1895 100000, &link);
1896 if (ret_val)
1897 return ret_val;
1898 }
1899
1900 if (hw->phy.type != e1000_phy_m88)
1901 return E1000_SUCCESS;
1902
1903 if (hw->phy.id == I347AT4_E_PHY_ID ||
1904 hw->phy.id == M88E1340M_E_PHY_ID ||
1905 hw->phy.id == M88E1112_E_PHY_ID)
1906 return E1000_SUCCESS;
1907 if (hw->phy.id == I210_I_PHY_ID)
1908 return E1000_SUCCESS;
1909 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1910 (hw->phy.id == M88E1512_E_PHY_ID))
1911 return E1000_SUCCESS;
1912 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1913 if (ret_val)
1914 return ret_val;
1915
1916 /* Resetting the phy means we need to re-force TX_CLK in the
1917 * Extended PHY Specific Control Register to 25MHz clock from
1918 * the reset value of 2.5MHz.
1919 */
1920 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1921 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1922 if (ret_val)
1923 return ret_val;
1924
1925 /* In addition, we must re-enable CRS on Tx for both half and full
1926 * duplex.
1927 */
1928 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1929 if (ret_val)
1930 return ret_val;
1931
1932 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1933 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1934
1935 return ret_val;
1936 }
1937
1938 /**
1939 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1940 * @hw: pointer to the HW structure
1941 *
1942 * Forces the speed and duplex settings of the PHY.
1943 * This is a function pointer entry point only called by
1944 * PHY setup routines.
1945 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1946 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1947 {
1948 struct e1000_phy_info *phy = &hw->phy;
1949 s32 ret_val;
1950 u16 data;
1951 bool link;
1952
1953 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1954
1955 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1956 if (ret_val)
1957 return ret_val;
1958
1959 e1000_phy_force_speed_duplex_setup(hw, &data);
1960
1961 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1962 if (ret_val)
1963 return ret_val;
1964
1965 /* Disable MDI-X support for 10/100 */
1966 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1967 if (ret_val)
1968 return ret_val;
1969
1970 data &= ~IFE_PMC_AUTO_MDIX;
1971 data &= ~IFE_PMC_FORCE_MDIX;
1972
1973 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1974 if (ret_val)
1975 return ret_val;
1976
1977 DEBUGOUT1("IFE PMC: %X\n", data);
1978
1979 usec_delay(1);
1980
1981 if (phy->autoneg_wait_to_complete) {
1982 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1983
1984 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1985 100000, &link);
1986 if (ret_val)
1987 return ret_val;
1988
1989 if (!link)
1990 DEBUGOUT("Link taking longer than expected.\n");
1991
1992 /* Try once more */
1993 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1994 100000, &link);
1995 if (ret_val)
1996 return ret_val;
1997 }
1998
1999 return E1000_SUCCESS;
2000 }
2001
2002 /**
2003 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2004 * @hw: pointer to the HW structure
2005 * @phy_ctrl: pointer to current value of PHY_CONTROL
2006 *
2007 * Forces speed and duplex on the PHY by doing the following: disable flow
2008 * control, force speed/duplex on the MAC, disable auto speed detection,
2009 * disable auto-negotiation, configure duplex, configure speed, configure
2010 * the collision distance, write configuration to CTRL register. The
2011 * caller must write to the PHY_CONTROL register for these settings to
2012 * take affect.
2013 **/
e1000_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)2014 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2015 {
2016 struct e1000_mac_info *mac = &hw->mac;
2017 u32 ctrl;
2018
2019 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2020
2021 /* Turn off flow control when forcing speed/duplex */
2022 hw->fc.current_mode = e1000_fc_none;
2023
2024 /* Force speed/duplex on the mac */
2025 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2026 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2027 ctrl &= ~E1000_CTRL_SPD_SEL;
2028
2029 /* Disable Auto Speed Detection */
2030 ctrl &= ~E1000_CTRL_ASDE;
2031
2032 /* Disable autoneg on the phy */
2033 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2034
2035 /* Forcing Full or Half Duplex? */
2036 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2037 ctrl &= ~E1000_CTRL_FD;
2038 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2039 DEBUGOUT("Half Duplex\n");
2040 } else {
2041 ctrl |= E1000_CTRL_FD;
2042 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2043 DEBUGOUT("Full Duplex\n");
2044 }
2045
2046 /* Forcing 10mb or 100mb? */
2047 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2048 ctrl |= E1000_CTRL_SPD_100;
2049 *phy_ctrl |= MII_CR_SPEED_100;
2050 *phy_ctrl &= ~MII_CR_SPEED_1000;
2051 DEBUGOUT("Forcing 100mb\n");
2052 } else {
2053 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2054 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2055 DEBUGOUT("Forcing 10mb\n");
2056 }
2057
2058 hw->mac.ops.config_collision_dist(hw);
2059
2060 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2061 }
2062
2063 /**
2064 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2065 * @hw: pointer to the HW structure
2066 * @active: boolean used to enable/disable lplu
2067 *
2068 * Success returns 0, Failure returns 1
2069 *
2070 * The low power link up (lplu) state is set to the power management level D3
2071 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
2072 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2073 * is used during Dx states where the power conservation is most important.
2074 * During driver activity, SmartSpeed should be enabled so performance is
2075 * maintained.
2076 **/
e1000_set_d3_lplu_state_generic(struct e1000_hw * hw,bool active)2077 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2078 {
2079 struct e1000_phy_info *phy = &hw->phy;
2080 s32 ret_val;
2081 u16 data;
2082
2083 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2084
2085 if (!hw->phy.ops.read_reg)
2086 return E1000_SUCCESS;
2087
2088 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2089 if (ret_val)
2090 return ret_val;
2091
2092 if (!active) {
2093 data &= ~IGP02E1000_PM_D3_LPLU;
2094 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2095 data);
2096 if (ret_val)
2097 return ret_val;
2098 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2099 * during Dx states where the power conservation is most
2100 * important. During driver activity we should enable
2101 * SmartSpeed, so performance is maintained.
2102 */
2103 if (phy->smart_speed == e1000_smart_speed_on) {
2104 ret_val = phy->ops.read_reg(hw,
2105 IGP01E1000_PHY_PORT_CONFIG,
2106 &data);
2107 if (ret_val)
2108 return ret_val;
2109
2110 data |= IGP01E1000_PSCFR_SMART_SPEED;
2111 ret_val = phy->ops.write_reg(hw,
2112 IGP01E1000_PHY_PORT_CONFIG,
2113 data);
2114 if (ret_val)
2115 return ret_val;
2116 } else if (phy->smart_speed == e1000_smart_speed_off) {
2117 ret_val = phy->ops.read_reg(hw,
2118 IGP01E1000_PHY_PORT_CONFIG,
2119 &data);
2120 if (ret_val)
2121 return ret_val;
2122
2123 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2124 ret_val = phy->ops.write_reg(hw,
2125 IGP01E1000_PHY_PORT_CONFIG,
2126 data);
2127 if (ret_val)
2128 return ret_val;
2129 }
2130 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2131 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2132 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2133 data |= IGP02E1000_PM_D3_LPLU;
2134 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2135 data);
2136 if (ret_val)
2137 return ret_val;
2138
2139 /* When LPLU is enabled, we should disable SmartSpeed */
2140 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2141 &data);
2142 if (ret_val)
2143 return ret_val;
2144
2145 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2146 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2147 data);
2148 }
2149
2150 return ret_val;
2151 }
2152
2153 /**
2154 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2155 * @hw: pointer to the HW structure
2156 *
2157 * Success returns 0, Failure returns 1
2158 *
2159 * A downshift is detected by querying the PHY link health.
2160 **/
e1000_check_downshift_generic(struct e1000_hw * hw)2161 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2162 {
2163 struct e1000_phy_info *phy = &hw->phy;
2164 s32 ret_val;
2165 u16 phy_data, offset, mask;
2166
2167 DEBUGFUNC("e1000_check_downshift_generic");
2168
2169 switch (phy->type) {
2170 case e1000_phy_i210:
2171 case e1000_phy_m88:
2172 case e1000_phy_gg82563:
2173 case e1000_phy_bm:
2174 case e1000_phy_82578:
2175 offset = M88E1000_PHY_SPEC_STATUS;
2176 mask = M88E1000_PSSR_DOWNSHIFT;
2177 break;
2178 case e1000_phy_igp:
2179 case e1000_phy_igp_2:
2180 case e1000_phy_igp_3:
2181 offset = IGP01E1000_PHY_LINK_HEALTH;
2182 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2183 break;
2184 default:
2185 /* speed downshift not supported */
2186 phy->speed_downgraded = FALSE;
2187 return E1000_SUCCESS;
2188 }
2189
2190 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2191
2192 if (!ret_val)
2193 phy->speed_downgraded = !!(phy_data & mask);
2194
2195 return ret_val;
2196 }
2197
2198 /**
2199 * e1000_check_polarity_m88 - Checks the polarity.
2200 * @hw: pointer to the HW structure
2201 *
2202 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2203 *
2204 * Polarity is determined based on the PHY specific status register.
2205 **/
e1000_check_polarity_m88(struct e1000_hw * hw)2206 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2207 {
2208 struct e1000_phy_info *phy = &hw->phy;
2209 s32 ret_val;
2210 u16 data;
2211
2212 DEBUGFUNC("e1000_check_polarity_m88");
2213
2214 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2215
2216 if (!ret_val)
2217 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2218 ? e1000_rev_polarity_reversed
2219 : e1000_rev_polarity_normal);
2220
2221 return ret_val;
2222 }
2223
2224 /**
2225 * e1000_check_polarity_igp - Checks the polarity.
2226 * @hw: pointer to the HW structure
2227 *
2228 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2229 *
2230 * Polarity is determined based on the PHY port status register, and the
2231 * current speed (since there is no polarity at 100Mbps).
2232 **/
e1000_check_polarity_igp(struct e1000_hw * hw)2233 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2234 {
2235 struct e1000_phy_info *phy = &hw->phy;
2236 s32 ret_val;
2237 u16 data, offset, mask;
2238
2239 DEBUGFUNC("e1000_check_polarity_igp");
2240
2241 /* Polarity is determined based on the speed of
2242 * our connection.
2243 */
2244 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2245 if (ret_val)
2246 return ret_val;
2247
2248 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2249 IGP01E1000_PSSR_SPEED_1000MBPS) {
2250 offset = IGP01E1000_PHY_PCS_INIT_REG;
2251 mask = IGP01E1000_PHY_POLARITY_MASK;
2252 } else {
2253 /* This really only applies to 10Mbps since
2254 * there is no polarity for 100Mbps (always 0).
2255 */
2256 offset = IGP01E1000_PHY_PORT_STATUS;
2257 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2258 }
2259
2260 ret_val = phy->ops.read_reg(hw, offset, &data);
2261
2262 if (!ret_val)
2263 phy->cable_polarity = ((data & mask)
2264 ? e1000_rev_polarity_reversed
2265 : e1000_rev_polarity_normal);
2266
2267 return ret_val;
2268 }
2269
2270 /**
2271 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2272 * @hw: pointer to the HW structure
2273 *
2274 * Polarity is determined on the polarity reversal feature being enabled.
2275 **/
e1000_check_polarity_ife(struct e1000_hw * hw)2276 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2277 {
2278 struct e1000_phy_info *phy = &hw->phy;
2279 s32 ret_val;
2280 u16 phy_data, offset, mask;
2281
2282 DEBUGFUNC("e1000_check_polarity_ife");
2283
2284 /* Polarity is determined based on the reversal feature being enabled.
2285 */
2286 if (phy->polarity_correction) {
2287 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2288 mask = IFE_PESC_POLARITY_REVERSED;
2289 } else {
2290 offset = IFE_PHY_SPECIAL_CONTROL;
2291 mask = IFE_PSC_FORCE_POLARITY;
2292 }
2293
2294 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2295
2296 if (!ret_val)
2297 phy->cable_polarity = ((phy_data & mask)
2298 ? e1000_rev_polarity_reversed
2299 : e1000_rev_polarity_normal);
2300
2301 return ret_val;
2302 }
2303
2304 /**
2305 * e1000_wait_autoneg - Wait for auto-neg completion
2306 * @hw: pointer to the HW structure
2307 *
2308 * Waits for auto-negotiation to complete or for the auto-negotiation time
2309 * limit to expire, which ever happens first.
2310 **/
e1000_wait_autoneg(struct e1000_hw * hw)2311 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2312 {
2313 s32 ret_val = E1000_SUCCESS;
2314 u16 i, phy_status;
2315
2316 DEBUGFUNC("e1000_wait_autoneg");
2317
2318 if (!hw->phy.ops.read_reg)
2319 return E1000_SUCCESS;
2320
2321 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2322 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2323 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2324 if (ret_val)
2325 break;
2326 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2327 if (ret_val)
2328 break;
2329 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2330 break;
2331 msec_delay(100);
2332 }
2333
2334 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2335 * has completed.
2336 */
2337 return ret_val;
2338 }
2339
2340 /**
2341 * e1000_phy_has_link_generic - Polls PHY for link
2342 * @hw: pointer to the HW structure
2343 * @iterations: number of times to poll for link
2344 * @usec_interval: delay between polling attempts
2345 * @success: pointer to whether polling was successful or not
2346 *
2347 * Polls the PHY status register for link, 'iterations' number of times.
2348 **/
e1000_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)2349 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2350 u32 usec_interval, bool *success)
2351 {
2352 s32 ret_val = E1000_SUCCESS;
2353 u16 i, phy_status;
2354
2355 DEBUGFUNC("e1000_phy_has_link_generic");
2356
2357 if (!hw->phy.ops.read_reg)
2358 return E1000_SUCCESS;
2359
2360 for (i = 0; i < iterations; i++) {
2361 /* Some PHYs require the PHY_STATUS register to be read
2362 * twice due to the link bit being sticky. No harm doing
2363 * it across the board.
2364 */
2365 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2366 if (ret_val) {
2367 /* If the first read fails, another entity may have
2368 * ownership of the resources, wait and try again to
2369 * see if they have relinquished the resources yet.
2370 */
2371 if (usec_interval >= 1000)
2372 msec_delay(usec_interval/1000);
2373 else
2374 usec_delay(usec_interval);
2375 }
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2377 if (ret_val)
2378 break;
2379 if (phy_status & MII_SR_LINK_STATUS)
2380 break;
2381 if (usec_interval >= 1000)
2382 msec_delay(usec_interval/1000);
2383 else
2384 usec_delay(usec_interval);
2385 }
2386
2387 *success = (i < iterations);
2388
2389 return ret_val;
2390 }
2391
2392 /**
2393 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2394 * @hw: pointer to the HW structure
2395 *
2396 * Reads the PHY specific status register to retrieve the cable length
2397 * information. The cable length is determined by averaging the minimum and
2398 * maximum values to get the "average" cable length. The m88 PHY has four
2399 * possible cable length values, which are:
2400 * Register Value Cable Length
2401 * 0 < 50 meters
2402 * 1 50 - 80 meters
2403 * 2 80 - 110 meters
2404 * 3 110 - 140 meters
2405 * 4 > 140 meters
2406 **/
e1000_get_cable_length_m88(struct e1000_hw * hw)2407 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2408 {
2409 struct e1000_phy_info *phy = &hw->phy;
2410 s32 ret_val;
2411 u16 phy_data, index;
2412
2413 DEBUGFUNC("e1000_get_cable_length_m88");
2414
2415 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2416 if (ret_val)
2417 return ret_val;
2418
2419 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2420 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2421
2422 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2423 return -E1000_ERR_PHY;
2424
2425 phy->min_cable_length = e1000_m88_cable_length_table[index];
2426 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2427
2428 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2429
2430 return E1000_SUCCESS;
2431 }
2432
e1000_get_cable_length_m88_gen2(struct e1000_hw * hw)2433 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2434 {
2435 struct e1000_phy_info *phy = &hw->phy;
2436 s32 ret_val;
2437 u16 phy_data, phy_data2, is_cm;
2438 u16 index, default_page;
2439
2440 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2441
2442 switch (hw->phy.id) {
2443 case I210_I_PHY_ID:
2444 /* Get cable length from PHY Cable Diagnostics Control Reg */
2445 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2446 (I347AT4_PCDL + phy->addr),
2447 &phy_data);
2448 if (ret_val)
2449 return ret_val;
2450
2451 /* Check if the unit of cable length is meters or cm */
2452 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2453 I347AT4_PCDC, &phy_data2);
2454 if (ret_val)
2455 return ret_val;
2456
2457 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2458
2459 /* Populate the phy structure with cable length in meters */
2460 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2461 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2463 break;
2464 case M88E1543_E_PHY_ID:
2465 case M88E1512_E_PHY_ID:
2466 case M88E1340M_E_PHY_ID:
2467 case I347AT4_E_PHY_ID:
2468 /* Remember the original page select and set it to 7 */
2469 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2470 &default_page);
2471 if (ret_val)
2472 return ret_val;
2473
2474 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2475 if (ret_val)
2476 return ret_val;
2477
2478 /* Get cable length from PHY Cable Diagnostics Control Reg */
2479 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2480 &phy_data);
2481 if (ret_val)
2482 return ret_val;
2483
2484 /* Check if the unit of cable length is meters or cm */
2485 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2486 if (ret_val)
2487 return ret_val;
2488
2489 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2490
2491 /* Populate the phy structure with cable length in meters */
2492 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2493 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2494 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2495
2496 /* Reset the page select to its original value */
2497 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2498 default_page);
2499 if (ret_val)
2500 return ret_val;
2501 break;
2502
2503 case M88E1112_E_PHY_ID:
2504 /* Remember the original page select and set it to 5 */
2505 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2506 &default_page);
2507 if (ret_val)
2508 return ret_val;
2509
2510 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2511 if (ret_val)
2512 return ret_val;
2513
2514 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2515 &phy_data);
2516 if (ret_val)
2517 return ret_val;
2518
2519 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2520 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2521
2522 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2523 return -E1000_ERR_PHY;
2524
2525 phy->min_cable_length = e1000_m88_cable_length_table[index];
2526 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2527
2528 phy->cable_length = (phy->min_cable_length +
2529 phy->max_cable_length) / 2;
2530
2531 /* Reset the page select to its original value */
2532 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2533 default_page);
2534 if (ret_val)
2535 return ret_val;
2536
2537 break;
2538 default:
2539 return -E1000_ERR_PHY;
2540 }
2541
2542 return ret_val;
2543 }
2544
2545 /**
2546 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2547 * @hw: pointer to the HW structure
2548 *
2549 * The automatic gain control (agc) normalizes the amplitude of the
2550 * received signal, adjusting for the attenuation produced by the
2551 * cable. By reading the AGC registers, which represent the
2552 * combination of coarse and fine gain value, the value can be put
2553 * into a lookup table to obtain the approximate cable length
2554 * for each channel.
2555 **/
e1000_get_cable_length_igp_2(struct e1000_hw * hw)2556 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2557 {
2558 struct e1000_phy_info *phy = &hw->phy;
2559 s32 ret_val;
2560 u16 phy_data, i, agc_value = 0;
2561 u16 cur_agc_index, max_agc_index = 0;
2562 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2563 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2564 IGP02E1000_PHY_AGC_A,
2565 IGP02E1000_PHY_AGC_B,
2566 IGP02E1000_PHY_AGC_C,
2567 IGP02E1000_PHY_AGC_D
2568 };
2569
2570 DEBUGFUNC("e1000_get_cable_length_igp_2");
2571
2572 /* Read the AGC registers for all channels */
2573 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2574 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2575 if (ret_val)
2576 return ret_val;
2577
2578 /* Getting bits 15:9, which represent the combination of
2579 * coarse and fine gain values. The result is a number
2580 * that can be put into the lookup table to obtain the
2581 * approximate cable length.
2582 */
2583 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2584 IGP02E1000_AGC_LENGTH_MASK);
2585
2586 /* Array index bound check. */
2587 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2588 (cur_agc_index == 0))
2589 return -E1000_ERR_PHY;
2590
2591 /* Remove min & max AGC values from calculation. */
2592 if (e1000_igp_2_cable_length_table[min_agc_index] >
2593 e1000_igp_2_cable_length_table[cur_agc_index])
2594 min_agc_index = cur_agc_index;
2595 if (e1000_igp_2_cable_length_table[max_agc_index] <
2596 e1000_igp_2_cable_length_table[cur_agc_index])
2597 max_agc_index = cur_agc_index;
2598
2599 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2600 }
2601
2602 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2603 e1000_igp_2_cable_length_table[max_agc_index]);
2604 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2605
2606 /* Calculate cable length with the error range of +/- 10 meters. */
2607 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2608 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2609 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2610
2611 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2612
2613 return E1000_SUCCESS;
2614 }
2615
2616 /**
2617 * e1000_get_phy_info_m88 - Retrieve PHY information
2618 * @hw: pointer to the HW structure
2619 *
2620 * Valid for only copper links. Read the PHY status register (sticky read)
2621 * to verify that link is up. Read the PHY special control register to
2622 * determine the polarity and 10base-T extended distance. Read the PHY
2623 * special status register to determine MDI/MDIx and current speed. If
2624 * speed is 1000, then determine cable length, local and remote receiver.
2625 **/
e1000_get_phy_info_m88(struct e1000_hw * hw)2626 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2627 {
2628 struct e1000_phy_info *phy = &hw->phy;
2629 s32 ret_val;
2630 u16 phy_data;
2631 bool link;
2632
2633 DEBUGFUNC("e1000_get_phy_info_m88");
2634
2635 if (phy->media_type != e1000_media_type_copper) {
2636 DEBUGOUT("Phy info is only valid for copper media\n");
2637 return -E1000_ERR_CONFIG;
2638 }
2639
2640 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2641 if (ret_val)
2642 return ret_val;
2643
2644 if (!link) {
2645 DEBUGOUT("Phy info is only valid if link is up\n");
2646 return -E1000_ERR_CONFIG;
2647 }
2648
2649 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2650 if (ret_val)
2651 return ret_val;
2652
2653 phy->polarity_correction = !!(phy_data &
2654 M88E1000_PSCR_POLARITY_REVERSAL);
2655
2656 ret_val = e1000_check_polarity_m88(hw);
2657 if (ret_val)
2658 return ret_val;
2659
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2661 if (ret_val)
2662 return ret_val;
2663
2664 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2665
2666 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2667 ret_val = hw->phy.ops.get_cable_length(hw);
2668 if (ret_val)
2669 return ret_val;
2670
2671 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2672 if (ret_val)
2673 return ret_val;
2674
2675 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2676 ? e1000_1000t_rx_status_ok
2677 : e1000_1000t_rx_status_not_ok;
2678
2679 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2680 ? e1000_1000t_rx_status_ok
2681 : e1000_1000t_rx_status_not_ok;
2682 } else {
2683 /* Set values to "undefined" */
2684 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2685 phy->local_rx = e1000_1000t_rx_status_undefined;
2686 phy->remote_rx = e1000_1000t_rx_status_undefined;
2687 }
2688
2689 return ret_val;
2690 }
2691
2692 /**
2693 * e1000_get_phy_info_igp - Retrieve igp PHY information
2694 * @hw: pointer to the HW structure
2695 *
2696 * Read PHY status to determine if link is up. If link is up, then
2697 * set/determine 10base-T extended distance and polarity correction. Read
2698 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2699 * determine on the cable length, local and remote receiver.
2700 **/
e1000_get_phy_info_igp(struct e1000_hw * hw)2701 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2702 {
2703 struct e1000_phy_info *phy = &hw->phy;
2704 s32 ret_val;
2705 u16 data;
2706 bool link;
2707
2708 DEBUGFUNC("e1000_get_phy_info_igp");
2709
2710 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2711 if (ret_val)
2712 return ret_val;
2713
2714 if (!link) {
2715 DEBUGOUT("Phy info is only valid if link is up\n");
2716 return -E1000_ERR_CONFIG;
2717 }
2718
2719 phy->polarity_correction = TRUE;
2720
2721 ret_val = e1000_check_polarity_igp(hw);
2722 if (ret_val)
2723 return ret_val;
2724
2725 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2726 if (ret_val)
2727 return ret_val;
2728
2729 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2730
2731 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2732 IGP01E1000_PSSR_SPEED_1000MBPS) {
2733 ret_val = phy->ops.get_cable_length(hw);
2734 if (ret_val)
2735 return ret_val;
2736
2737 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2738 if (ret_val)
2739 return ret_val;
2740
2741 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2742 ? e1000_1000t_rx_status_ok
2743 : e1000_1000t_rx_status_not_ok;
2744
2745 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2746 ? e1000_1000t_rx_status_ok
2747 : e1000_1000t_rx_status_not_ok;
2748 } else {
2749 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2750 phy->local_rx = e1000_1000t_rx_status_undefined;
2751 phy->remote_rx = e1000_1000t_rx_status_undefined;
2752 }
2753
2754 return ret_val;
2755 }
2756
2757 /**
2758 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2759 * @hw: pointer to the HW structure
2760 *
2761 * Populates "phy" structure with various feature states.
2762 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2763 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2764 {
2765 struct e1000_phy_info *phy = &hw->phy;
2766 s32 ret_val;
2767 u16 data;
2768 bool link;
2769
2770 DEBUGFUNC("e1000_get_phy_info_ife");
2771
2772 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2773 if (ret_val)
2774 return ret_val;
2775
2776 if (!link) {
2777 DEBUGOUT("Phy info is only valid if link is up\n");
2778 return -E1000_ERR_CONFIG;
2779 }
2780
2781 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2782 if (ret_val)
2783 return ret_val;
2784 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2785
2786 if (phy->polarity_correction) {
2787 ret_val = e1000_check_polarity_ife(hw);
2788 if (ret_val)
2789 return ret_val;
2790 } else {
2791 /* Polarity is forced */
2792 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2793 ? e1000_rev_polarity_reversed
2794 : e1000_rev_polarity_normal);
2795 }
2796
2797 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2798 if (ret_val)
2799 return ret_val;
2800
2801 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2802
2803 /* The following parameters are undefined for 10/100 operation. */
2804 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2805 phy->local_rx = e1000_1000t_rx_status_undefined;
2806 phy->remote_rx = e1000_1000t_rx_status_undefined;
2807
2808 return E1000_SUCCESS;
2809 }
2810
2811 /**
2812 * e1000_phy_sw_reset_generic - PHY software reset
2813 * @hw: pointer to the HW structure
2814 *
2815 * Does a software reset of the PHY by reading the PHY control register and
2816 * setting/write the control register reset bit to the PHY.
2817 **/
e1000_phy_sw_reset_generic(struct e1000_hw * hw)2818 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2819 {
2820 s32 ret_val;
2821 u16 phy_ctrl;
2822
2823 DEBUGFUNC("e1000_phy_sw_reset_generic");
2824
2825 if (!hw->phy.ops.read_reg)
2826 return E1000_SUCCESS;
2827
2828 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2829 if (ret_val)
2830 return ret_val;
2831
2832 phy_ctrl |= MII_CR_RESET;
2833 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2834 if (ret_val)
2835 return ret_val;
2836
2837 usec_delay(1);
2838
2839 return ret_val;
2840 }
2841
2842 /**
2843 * e1000_phy_hw_reset_generic - PHY hardware reset
2844 * @hw: pointer to the HW structure
2845 *
2846 * Verify the reset block is not blocking us from resetting. Acquire
2847 * semaphore (if necessary) and read/set/write the device control reset
2848 * bit in the PHY. Wait the appropriate delay time for the device to
2849 * reset and release the semaphore (if necessary).
2850 **/
e1000_phy_hw_reset_generic(struct e1000_hw * hw)2851 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2852 {
2853 struct e1000_phy_info *phy = &hw->phy;
2854 s32 ret_val;
2855 u32 ctrl;
2856
2857 DEBUGFUNC("e1000_phy_hw_reset_generic");
2858
2859 if (phy->ops.check_reset_block) {
2860 ret_val = phy->ops.check_reset_block(hw);
2861 if (ret_val)
2862 return E1000_SUCCESS;
2863 }
2864
2865 ret_val = phy->ops.acquire(hw);
2866 if (ret_val)
2867 return ret_val;
2868
2869 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2870 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2871 E1000_WRITE_FLUSH(hw);
2872
2873 usec_delay(phy->reset_delay_us);
2874
2875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2876 E1000_WRITE_FLUSH(hw);
2877
2878 usec_delay(150);
2879
2880 phy->ops.release(hw);
2881
2882 return phy->ops.get_cfg_done(hw);
2883 }
2884
2885 /**
2886 * e1000_get_cfg_done_generic - Generic configuration done
2887 * @hw: pointer to the HW structure
2888 *
2889 * Generic function to wait 10 milli-seconds for configuration to complete
2890 * and return success.
2891 **/
e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG * hw)2892 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2893 {
2894 DEBUGFUNC("e1000_get_cfg_done_generic");
2895
2896 msec_delay_irq(10);
2897
2898 return E1000_SUCCESS;
2899 }
2900
2901 /**
2902 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2903 * @hw: pointer to the HW structure
2904 *
2905 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2906 **/
e1000_phy_init_script_igp3(struct e1000_hw * hw)2907 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2908 {
2909 DEBUGOUT("Running IGP 3 PHY init script\n");
2910
2911 /* PHY init IGP 3 */
2912 /* Enable rise/fall, 10-mode work in class-A */
2913 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2914 /* Remove all caps from Replica path filter */
2915 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2916 /* Bias trimming for ADC, AFE and Driver (Default) */
2917 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2918 /* Increase Hybrid poly bias */
2919 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2920 /* Add 4% to Tx amplitude in Gig mode */
2921 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2922 /* Disable trimming (TTT) */
2923 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2924 /* Poly DC correction to 94.6% + 2% for all channels */
2925 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2926 /* ABS DC correction to 95.9% */
2927 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2928 /* BG temp curve trim */
2929 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2930 /* Increasing ADC OPAMP stage 1 currents to max */
2931 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2932 /* Force 1000 ( required for enabling PHY regs configuration) */
2933 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2934 /* Set upd_freq to 6 */
2935 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2936 /* Disable NPDFE */
2937 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2938 /* Disable adaptive fixed FFE (Default) */
2939 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2940 /* Enable FFE hysteresis */
2941 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2942 /* Fixed FFE for short cable lengths */
2943 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2944 /* Fixed FFE for medium cable lengths */
2945 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2946 /* Fixed FFE for long cable lengths */
2947 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2948 /* Enable Adaptive Clip Threshold */
2949 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2950 /* AHT reset limit to 1 */
2951 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2952 /* Set AHT master delay to 127 msec */
2953 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2954 /* Set scan bits for AHT */
2955 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2956 /* Set AHT Preset bits */
2957 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2958 /* Change integ_factor of channel A to 3 */
2959 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2960 /* Change prop_factor of channels BCD to 8 */
2961 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2962 /* Change cg_icount + enable integbp for channels BCD */
2963 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2964 /* Change cg_icount + enable integbp + change prop_factor_master
2965 * to 8 for channel A
2966 */
2967 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2968 /* Disable AHT in Slave mode on channel A */
2969 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2970 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2971 * Enable SPD+B2B
2972 */
2973 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2974 /* Enable restart AN on an1000_dis change */
2975 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2976 /* Enable wh_fifo read clock in 10/100 modes */
2977 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2978 /* Restart AN, Speed selection is 1000 */
2979 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2980
2981 return E1000_SUCCESS;
2982 }
2983
2984 /**
2985 * e1000_get_phy_type_from_id - Get PHY type from id
2986 * @phy_id: phy_id read from the phy
2987 *
2988 * Returns the phy type from the id.
2989 **/
e1000_get_phy_type_from_id(u32 phy_id)2990 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2991 {
2992 enum e1000_phy_type phy_type = e1000_phy_unknown;
2993
2994 switch (phy_id) {
2995 case M88E1000_I_PHY_ID:
2996 case M88E1000_E_PHY_ID:
2997 case M88E1111_I_PHY_ID:
2998 case M88E1011_I_PHY_ID:
2999 case M88E1543_E_PHY_ID:
3000 case M88E1512_E_PHY_ID:
3001 case I347AT4_E_PHY_ID:
3002 case M88E1112_E_PHY_ID:
3003 case M88E1340M_E_PHY_ID:
3004 phy_type = e1000_phy_m88;
3005 break;
3006 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3007 phy_type = e1000_phy_igp_2;
3008 break;
3009 case GG82563_E_PHY_ID:
3010 phy_type = e1000_phy_gg82563;
3011 break;
3012 case IGP03E1000_E_PHY_ID:
3013 phy_type = e1000_phy_igp_3;
3014 break;
3015 case IFE_E_PHY_ID:
3016 case IFE_PLUS_E_PHY_ID:
3017 case IFE_C_E_PHY_ID:
3018 phy_type = e1000_phy_ife;
3019 break;
3020 case BME1000_E_PHY_ID:
3021 case BME1000_E_PHY_ID_R2:
3022 phy_type = e1000_phy_bm;
3023 break;
3024 case I82578_E_PHY_ID:
3025 phy_type = e1000_phy_82578;
3026 break;
3027 case I82577_E_PHY_ID:
3028 phy_type = e1000_phy_82577;
3029 break;
3030 case I82579_E_PHY_ID:
3031 phy_type = e1000_phy_82579;
3032 break;
3033 case I217_E_PHY_ID:
3034 phy_type = e1000_phy_i217;
3035 break;
3036 case I82580_I_PHY_ID:
3037 phy_type = e1000_phy_82580;
3038 break;
3039 case I210_I_PHY_ID:
3040 phy_type = e1000_phy_i210;
3041 break;
3042 default:
3043 phy_type = e1000_phy_unknown;
3044 break;
3045 }
3046 return phy_type;
3047 }
3048
3049 /**
3050 * e1000_determine_phy_address - Determines PHY address.
3051 * @hw: pointer to the HW structure
3052 *
3053 * This uses a trial and error method to loop through possible PHY
3054 * addresses. It tests each by reading the PHY ID registers and
3055 * checking for a match.
3056 **/
e1000_determine_phy_address(struct e1000_hw * hw)3057 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3058 {
3059 u32 phy_addr = 0;
3060 u32 i;
3061 enum e1000_phy_type phy_type = e1000_phy_unknown;
3062
3063 hw->phy.id = phy_type;
3064
3065 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3066 hw->phy.addr = phy_addr;
3067 i = 0;
3068
3069 do {
3070 e1000_get_phy_id(hw);
3071 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3072
3073 /* If phy_type is valid, break - we found our
3074 * PHY address
3075 */
3076 if (phy_type != e1000_phy_unknown)
3077 return E1000_SUCCESS;
3078
3079 msec_delay(1);
3080 i++;
3081 } while (i < 10);
3082 }
3083
3084 return -E1000_ERR_PHY_TYPE;
3085 }
3086
3087 /**
3088 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3089 * @page: page to access
3090 *
3091 * Returns the phy address for the page requested.
3092 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)3093 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3094 {
3095 u32 phy_addr = 2;
3096
3097 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3098 phy_addr = 1;
3099
3100 return phy_addr;
3101 }
3102
3103 /**
3104 * e1000_write_phy_reg_bm - Write BM PHY register
3105 * @hw: pointer to the HW structure
3106 * @offset: register offset to write to
3107 * @data: data to write at register offset
3108 *
3109 * Acquires semaphore, if necessary, then writes the data to PHY register
3110 * at the offset. Release any acquired semaphores before exiting.
3111 **/
e1000_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)3112 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3113 {
3114 s32 ret_val;
3115 u32 page = offset >> IGP_PAGE_SHIFT;
3116
3117 DEBUGFUNC("e1000_write_phy_reg_bm");
3118
3119 ret_val = hw->phy.ops.acquire(hw);
3120 if (ret_val)
3121 return ret_val;
3122
3123 /* Page 800 works differently than the rest so it has its own func */
3124 if (page == BM_WUC_PAGE) {
3125 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3126 FALSE, false);
3127 goto release;
3128 }
3129
3130 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3131
3132 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3133 u32 page_shift, page_select;
3134
3135 /* Page select is register 31 for phy address 1 and 22 for
3136 * phy address 2 and 3. Page select is shifted only for
3137 * phy address 1.
3138 */
3139 if (hw->phy.addr == 1) {
3140 page_shift = IGP_PAGE_SHIFT;
3141 page_select = IGP01E1000_PHY_PAGE_SELECT;
3142 } else {
3143 page_shift = 0;
3144 page_select = BM_PHY_PAGE_SELECT;
3145 }
3146
3147 /* Page is shifted left, PHY expects (page x 32) */
3148 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3149 (page << page_shift));
3150 if (ret_val)
3151 goto release;
3152 }
3153
3154 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3155 data);
3156
3157 release:
3158 hw->phy.ops.release(hw);
3159 return ret_val;
3160 }
3161
3162 /**
3163 * e1000_read_phy_reg_bm - Read BM PHY register
3164 * @hw: pointer to the HW structure
3165 * @offset: register offset to be read
3166 * @data: pointer to the read data
3167 *
3168 * Acquires semaphore, if necessary, then reads the PHY register at offset
3169 * and storing the retrieved information in data. Release any acquired
3170 * semaphores before exiting.
3171 **/
e1000_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)3172 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3173 {
3174 s32 ret_val;
3175 u32 page = offset >> IGP_PAGE_SHIFT;
3176
3177 DEBUGFUNC("e1000_read_phy_reg_bm");
3178
3179 ret_val = hw->phy.ops.acquire(hw);
3180 if (ret_val)
3181 return ret_val;
3182
3183 /* Page 800 works differently than the rest so it has its own func */
3184 if (page == BM_WUC_PAGE) {
3185 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3186 TRUE, FALSE);
3187 goto release;
3188 }
3189
3190 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3191
3192 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3193 u32 page_shift, page_select;
3194
3195 /* Page select is register 31 for phy address 1 and 22 for
3196 * phy address 2 and 3. Page select is shifted only for
3197 * phy address 1.
3198 */
3199 if (hw->phy.addr == 1) {
3200 page_shift = IGP_PAGE_SHIFT;
3201 page_select = IGP01E1000_PHY_PAGE_SELECT;
3202 } else {
3203 page_shift = 0;
3204 page_select = BM_PHY_PAGE_SELECT;
3205 }
3206
3207 /* Page is shifted left, PHY expects (page x 32) */
3208 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3209 (page << page_shift));
3210 if (ret_val)
3211 goto release;
3212 }
3213
3214 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3215 data);
3216 release:
3217 hw->phy.ops.release(hw);
3218 return ret_val;
3219 }
3220
3221 /**
3222 * e1000_read_phy_reg_bm2 - Read BM PHY register
3223 * @hw: pointer to the HW structure
3224 * @offset: register offset to be read
3225 * @data: pointer to the read data
3226 *
3227 * Acquires semaphore, if necessary, then reads the PHY register at offset
3228 * and storing the retrieved information in data. Release any acquired
3229 * semaphores before exiting.
3230 **/
e1000_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)3231 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3232 {
3233 s32 ret_val;
3234 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3235
3236 DEBUGFUNC("e1000_read_phy_reg_bm2");
3237
3238 ret_val = hw->phy.ops.acquire(hw);
3239 if (ret_val)
3240 return ret_val;
3241
3242 /* Page 800 works differently than the rest so it has its own func */
3243 if (page == BM_WUC_PAGE) {
3244 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3245 TRUE, FALSE);
3246 goto release;
3247 }
3248
3249 hw->phy.addr = 1;
3250
3251 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3252 /* Page is shifted left, PHY expects (page x 32) */
3253 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3254 page);
3255
3256 if (ret_val)
3257 goto release;
3258 }
3259
3260 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3261 data);
3262 release:
3263 hw->phy.ops.release(hw);
3264 return ret_val;
3265 }
3266
3267 /**
3268 * e1000_write_phy_reg_bm2 - Write BM PHY register
3269 * @hw: pointer to the HW structure
3270 * @offset: register offset to write to
3271 * @data: data to write at register offset
3272 *
3273 * Acquires semaphore, if necessary, then writes the data to PHY register
3274 * at the offset. Release any acquired semaphores before exiting.
3275 **/
e1000_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)3276 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3277 {
3278 s32 ret_val;
3279 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3280
3281 DEBUGFUNC("e1000_write_phy_reg_bm2");
3282
3283 ret_val = hw->phy.ops.acquire(hw);
3284 if (ret_val)
3285 return ret_val;
3286
3287 /* Page 800 works differently than the rest so it has its own func */
3288 if (page == BM_WUC_PAGE) {
3289 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3290 FALSE, false);
3291 goto release;
3292 }
3293
3294 hw->phy.addr = 1;
3295
3296 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3297 /* Page is shifted left, PHY expects (page x 32) */
3298 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3299 page);
3300
3301 if (ret_val)
3302 goto release;
3303 }
3304
3305 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3306 data);
3307
3308 release:
3309 hw->phy.ops.release(hw);
3310 return ret_val;
3311 }
3312
3313 /**
3314 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3315 * @hw: pointer to the HW structure
3316 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3317 *
3318 * Assumes semaphore already acquired and phy_reg points to a valid memory
3319 * address to store contents of the BM_WUC_ENABLE_REG register.
3320 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3321 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3322 {
3323 s32 ret_val;
3324 u16 temp;
3325
3326 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3327
3328 if (!phy_reg)
3329 return -E1000_ERR_PARAM;
3330
3331 /* All page select, port ctrl and wakeup registers use phy address 1 */
3332 hw->phy.addr = 1;
3333
3334 /* Select Port Control Registers page */
3335 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3336 if (ret_val) {
3337 DEBUGOUT("Could not set Port Control page\n");
3338 return ret_val;
3339 }
3340
3341 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3342 if (ret_val) {
3343 DEBUGOUT2("Could not read PHY register %d.%d\n",
3344 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3345 return ret_val;
3346 }
3347
3348 /* Enable both PHY wakeup mode and Wakeup register page writes.
3349 * Prevent a power state change by disabling ME and Host PHY wakeup.
3350 */
3351 temp = *phy_reg;
3352 temp |= BM_WUC_ENABLE_BIT;
3353 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3354
3355 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3356 if (ret_val) {
3357 DEBUGOUT2("Could not write PHY register %d.%d\n",
3358 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3359 return ret_val;
3360 }
3361
3362 /* Select Host Wakeup Registers page - caller now able to write
3363 * registers on the Wakeup registers page
3364 */
3365 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3366 }
3367
3368 /**
3369 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3370 * @hw: pointer to the HW structure
3371 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3372 *
3373 * Restore BM_WUC_ENABLE_REG to its original value.
3374 *
3375 * Assumes semaphore already acquired and *phy_reg is the contents of the
3376 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3377 * caller.
3378 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3379 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3380 {
3381 s32 ret_val;
3382
3383 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3384
3385 if (!phy_reg)
3386 return -E1000_ERR_PARAM;
3387
3388 /* Select Port Control Registers page */
3389 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3390 if (ret_val) {
3391 DEBUGOUT("Could not set Port Control page\n");
3392 return ret_val;
3393 }
3394
3395 /* Restore 769.17 to its original value */
3396 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3397 if (ret_val)
3398 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3399 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3400
3401 return ret_val;
3402 }
3403
3404 /**
3405 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3406 * @hw: pointer to the HW structure
3407 * @offset: register offset to be read or written
3408 * @data: pointer to the data to read or write
3409 * @read: determines if operation is read or write
3410 * @page_set: BM_WUC_PAGE already set and access enabled
3411 *
3412 * Read the PHY register at offset and store the retrieved information in
3413 * data, or write data to PHY register at offset. Note the procedure to
3414 * access the PHY wakeup registers is different than reading the other PHY
3415 * registers. It works as such:
3416 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3417 * 2) Set page to 800 for host (801 if we were manageability)
3418 * 3) Write the address using the address opcode (0x11)
3419 * 4) Read or write the data using the data opcode (0x12)
3420 * 5) Restore 769.17.2 to its original value
3421 *
3422 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3423 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3424 *
3425 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3426 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3427 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3428 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)3429 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3430 u16 *data, bool read, bool page_set)
3431 {
3432 s32 ret_val;
3433 u16 reg = BM_PHY_REG_NUM(offset);
3434 u16 page = BM_PHY_REG_PAGE(offset);
3435 u16 phy_reg = 0;
3436
3437 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3438
3439 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3440 if ((hw->mac.type == e1000_pchlan) &&
3441 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3442 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3443 page);
3444
3445 if (!page_set) {
3446 /* Enable access to PHY wakeup registers */
3447 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3448 if (ret_val) {
3449 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3450 return ret_val;
3451 }
3452 }
3453
3454 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3455
3456 /* Write the Wakeup register page offset value using opcode 0x11 */
3457 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3458 if (ret_val) {
3459 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3460 return ret_val;
3461 }
3462
3463 if (read) {
3464 /* Read the Wakeup register page value using opcode 0x12 */
3465 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3466 data);
3467 } else {
3468 /* Write the Wakeup register page value using opcode 0x12 */
3469 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3470 *data);
3471 }
3472
3473 if (ret_val) {
3474 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3475 return ret_val;
3476 }
3477
3478 if (!page_set)
3479 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3480
3481 return ret_val;
3482 }
3483
3484 /**
3485 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3486 * @hw: pointer to the HW structure
3487 *
3488 * In the case of a PHY power down to save power, or to turn off link during a
3489 * driver unload, or wake on lan is not enabled, restore the link to previous
3490 * settings.
3491 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)3492 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3493 {
3494 u16 mii_reg = 0;
3495
3496 /* The PHY will retain its settings across a power down/up cycle */
3497 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3498 mii_reg &= ~MII_CR_POWER_DOWN;
3499 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3500 }
3501
3502 /**
3503 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3504 * @hw: pointer to the HW structure
3505 *
3506 * In the case of a PHY power down to save power, or to turn off link during a
3507 * driver unload, or wake on lan is not enabled, restore the link to previous
3508 * settings.
3509 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)3510 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3511 {
3512 u16 mii_reg = 0;
3513
3514 /* The PHY will retain its settings across a power down/up cycle */
3515 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3516 mii_reg |= MII_CR_POWER_DOWN;
3517 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3518 msec_delay(1);
3519 }
3520
3521 /**
3522 * __e1000_read_phy_reg_hv - Read HV PHY register
3523 * @hw: pointer to the HW structure
3524 * @offset: register offset to be read
3525 * @data: pointer to the read data
3526 * @locked: semaphore has already been acquired or not
3527 *
3528 * Acquires semaphore, if necessary, then reads the PHY register at offset
3529 * and stores the retrieved information in data. Release any acquired
3530 * semaphore before exiting.
3531 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)3532 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3533 bool locked, bool page_set)
3534 {
3535 s32 ret_val;
3536 u16 page = BM_PHY_REG_PAGE(offset);
3537 u16 reg = BM_PHY_REG_NUM(offset);
3538 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3539
3540 DEBUGFUNC("__e1000_read_phy_reg_hv");
3541
3542 if (!locked) {
3543 ret_val = hw->phy.ops.acquire(hw);
3544 if (ret_val)
3545 return ret_val;
3546 }
3547 /* Page 800 works differently than the rest so it has its own func */
3548 if (page == BM_WUC_PAGE) {
3549 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3550 TRUE, page_set);
3551 goto out;
3552 }
3553
3554 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3555 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3556 data, TRUE);
3557 goto out;
3558 }
3559
3560 if (!page_set) {
3561 if (page == HV_INTC_FC_PAGE_START)
3562 page = 0;
3563
3564 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3565 /* Page is shifted left, PHY expects (page x 32) */
3566 ret_val = e1000_set_page_igp(hw,
3567 (page << IGP_PAGE_SHIFT));
3568
3569 hw->phy.addr = phy_addr;
3570
3571 if (ret_val)
3572 goto out;
3573 }
3574 }
3575
3576 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3577 page << IGP_PAGE_SHIFT, reg);
3578
3579 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3580 data);
3581 out:
3582 if (!locked)
3583 hw->phy.ops.release(hw);
3584
3585 return ret_val;
3586 }
3587
3588 /**
3589 * e1000_read_phy_reg_hv - Read HV PHY register
3590 * @hw: pointer to the HW structure
3591 * @offset: register offset to be read
3592 * @data: pointer to the read data
3593 *
3594 * Acquires semaphore then reads the PHY register at offset and stores
3595 * the retrieved information in data. Release the acquired semaphore
3596 * before exiting.
3597 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)3598 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3599 {
3600 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false);
3601 }
3602
3603 /**
3604 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3605 * @hw: pointer to the HW structure
3606 * @offset: register offset to be read
3607 * @data: pointer to the read data
3608 *
3609 * Reads the PHY register at offset and stores the retrieved information
3610 * in data. Assumes semaphore already acquired.
3611 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)3612 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3613 {
3614 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3615 }
3616
3617 /**
3618 * e1000_read_phy_reg_page_hv - Read HV PHY register
3619 * @hw: pointer to the HW structure
3620 * @offset: register offset to write to
3621 * @data: data to write at register offset
3622 *
3623 * Reads the PHY register at offset and stores the retrieved information
3624 * in data. Assumes semaphore already acquired and page already set.
3625 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)3626 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3627 {
3628 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3629 }
3630
3631 /**
3632 * __e1000_write_phy_reg_hv - Write HV PHY register
3633 * @hw: pointer to the HW structure
3634 * @offset: register offset to write to
3635 * @data: data to write at register offset
3636 * @locked: semaphore has already been acquired or not
3637 *
3638 * Acquires semaphore, if necessary, then writes the data to PHY register
3639 * at the offset. Release any acquired semaphores before exiting.
3640 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)3641 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3642 bool locked, bool page_set)
3643 {
3644 s32 ret_val;
3645 u16 page = BM_PHY_REG_PAGE(offset);
3646 u16 reg = BM_PHY_REG_NUM(offset);
3647 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3648
3649 DEBUGFUNC("__e1000_write_phy_reg_hv");
3650
3651 if (!locked) {
3652 ret_val = hw->phy.ops.acquire(hw);
3653 if (ret_val)
3654 return ret_val;
3655 }
3656 /* Page 800 works differently than the rest so it has its own func */
3657 if (page == BM_WUC_PAGE) {
3658 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3659 FALSE, page_set);
3660 goto out;
3661 }
3662
3663 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3664 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3665 &data, FALSE);
3666 goto out;
3667 }
3668
3669 if (!page_set) {
3670 if (page == HV_INTC_FC_PAGE_START)
3671 page = 0;
3672
3673 /* Workaround MDIO accesses being disabled after entering IEEE
3674 * Power Down (when bit 11 of the PHY Control register is set)
3675 */
3676 if ((hw->phy.type == e1000_phy_82578) &&
3677 (hw->phy.revision >= 1) &&
3678 (hw->phy.addr == 2) &&
3679 !(MAX_PHY_REG_ADDRESS & reg) &&
3680 (data & (1 << 11))) {
3681 u16 data2 = 0x7EFF;
3682 ret_val = e1000_access_phy_debug_regs_hv(hw,
3683 (1 << 6) | 0x3,
3684 &data2, FALSE);
3685 if (ret_val)
3686 goto out;
3687 }
3688
3689 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3690 /* Page is shifted left, PHY expects (page x 32) */
3691 ret_val = e1000_set_page_igp(hw,
3692 (page << IGP_PAGE_SHIFT));
3693
3694 hw->phy.addr = phy_addr;
3695
3696 if (ret_val)
3697 goto out;
3698 }
3699 }
3700
3701 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3702 page << IGP_PAGE_SHIFT, reg);
3703
3704 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3705 data);
3706
3707 out:
3708 if (!locked)
3709 hw->phy.ops.release(hw);
3710
3711 return ret_val;
3712 }
3713
3714 /**
3715 * e1000_write_phy_reg_hv - Write HV PHY register
3716 * @hw: pointer to the HW structure
3717 * @offset: register offset to write to
3718 * @data: data to write at register offset
3719 *
3720 * Acquires semaphore then writes the data to PHY register at the offset.
3721 * Release the acquired semaphores before exiting.
3722 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)3723 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3724 {
3725 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false);
3726 }
3727
3728 /**
3729 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3730 * @hw: pointer to the HW structure
3731 * @offset: register offset to write to
3732 * @data: data to write at register offset
3733 *
3734 * Writes the data to PHY register at the offset. Assumes semaphore
3735 * already acquired.
3736 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3737 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3738 {
3739 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3740 }
3741
3742 /**
3743 * e1000_write_phy_reg_page_hv - Write HV PHY register
3744 * @hw: pointer to the HW structure
3745 * @offset: register offset to write to
3746 * @data: data to write at register offset
3747 *
3748 * Writes the data to PHY register at the offset. Assumes semaphore
3749 * already acquired and page already set.
3750 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)3751 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3752 {
3753 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3754 }
3755
3756 /**
3757 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3758 * @page: page to be accessed
3759 **/
e1000_get_phy_addr_for_hv_page(u32 page)3760 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3761 {
3762 u32 phy_addr = 2;
3763
3764 if (page >= HV_INTC_FC_PAGE_START)
3765 phy_addr = 1;
3766
3767 return phy_addr;
3768 }
3769
3770 /**
3771 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3772 * @hw: pointer to the HW structure
3773 * @offset: register offset to be read or written
3774 * @data: pointer to the data to be read or written
3775 * @read: determines if operation is read or write
3776 *
3777 * Reads the PHY register at offset and stores the retreived information
3778 * in data. Assumes semaphore already acquired. Note that the procedure
3779 * to access these regs uses the address port and data port to read/write.
3780 * These accesses done with PHY address 2 and without using pages.
3781 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3782 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3783 u16 *data, bool read)
3784 {
3785 s32 ret_val;
3786 u32 addr_reg;
3787 u32 data_reg;
3788
3789 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3790
3791 /* This takes care of the difference with desktop vs mobile phy */
3792 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3793 I82578_ADDR_REG : I82577_ADDR_REG);
3794 data_reg = addr_reg + 1;
3795
3796 /* All operations in this function are phy address 2 */
3797 hw->phy.addr = 2;
3798
3799 /* masking with 0x3F to remove the page from offset */
3800 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3801 if (ret_val) {
3802 DEBUGOUT("Could not write the Address Offset port register\n");
3803 return ret_val;
3804 }
3805
3806 /* Read or write the data value next */
3807 if (read)
3808 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3809 else
3810 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3811
3812 if (ret_val)
3813 DEBUGOUT("Could not access the Data port register\n");
3814
3815 return ret_val;
3816 }
3817
3818 /**
3819 * e1000_link_stall_workaround_hv - Si workaround
3820 * @hw: pointer to the HW structure
3821 *
3822 * This function works around a Si bug where the link partner can get
3823 * a link up indication before the PHY does. If small packets are sent
3824 * by the link partner they can be placed in the packet buffer without
3825 * being properly accounted for by the PHY and will stall preventing
3826 * further packets from being received. The workaround is to clear the
3827 * packet buffer after the PHY detects link up.
3828 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3829 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3830 {
3831 s32 ret_val = E1000_SUCCESS;
3832 u16 data;
3833
3834 DEBUGFUNC("e1000_link_stall_workaround_hv");
3835
3836 if (hw->phy.type != e1000_phy_82578)
3837 return E1000_SUCCESS;
3838
3839 /* Do not apply workaround if in PHY loopback bit 14 set */
3840 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3841 if (data & PHY_CONTROL_LB)
3842 return E1000_SUCCESS;
3843
3844 /* check if link is up and at 1Gbps */
3845 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3846 if (ret_val)
3847 return ret_val;
3848
3849 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3850 BM_CS_STATUS_SPEED_MASK);
3851
3852 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3853 BM_CS_STATUS_SPEED_1000))
3854 return E1000_SUCCESS;
3855
3856 msec_delay(200);
3857
3858 /* flush the packets in the fifo buffer */
3859 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3860 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3861 HV_MUX_DATA_CTRL_FORCE_SPEED));
3862 if (ret_val)
3863 return ret_val;
3864
3865 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3866 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3867 }
3868
3869 /**
3870 * e1000_check_polarity_82577 - Checks the polarity.
3871 * @hw: pointer to the HW structure
3872 *
3873 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3874 *
3875 * Polarity is determined based on the PHY specific status register.
3876 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3877 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3878 {
3879 struct e1000_phy_info *phy = &hw->phy;
3880 s32 ret_val;
3881 u16 data;
3882
3883 DEBUGFUNC("e1000_check_polarity_82577");
3884
3885 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3886
3887 if (!ret_val)
3888 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3889 ? e1000_rev_polarity_reversed
3890 : e1000_rev_polarity_normal);
3891
3892 return ret_val;
3893 }
3894
3895 /**
3896 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3897 * @hw: pointer to the HW structure
3898 *
3899 * Calls the PHY setup function to force speed and duplex.
3900 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3901 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3902 {
3903 struct e1000_phy_info *phy = &hw->phy;
3904 s32 ret_val;
3905 u16 phy_data;
3906 bool link;
3907
3908 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3909
3910 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3911 if (ret_val)
3912 return ret_val;
3913
3914 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3915
3916 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3917 if (ret_val)
3918 return ret_val;
3919
3920 usec_delay(1);
3921
3922 if (phy->autoneg_wait_to_complete) {
3923 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3924
3925 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3926 100000, &link);
3927 if (ret_val)
3928 return ret_val;
3929
3930 if (!link)
3931 DEBUGOUT("Link taking longer than expected.\n");
3932
3933 /* Try once more */
3934 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3935 100000, &link);
3936 }
3937
3938 return ret_val;
3939 }
3940
3941 /**
3942 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3943 * @hw: pointer to the HW structure
3944 *
3945 * Read PHY status to determine if link is up. If link is up, then
3946 * set/determine 10base-T extended distance and polarity correction. Read
3947 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3948 * determine on the cable length, local and remote receiver.
3949 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3950 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3951 {
3952 struct e1000_phy_info *phy = &hw->phy;
3953 s32 ret_val;
3954 u16 data;
3955 bool link;
3956
3957 DEBUGFUNC("e1000_get_phy_info_82577");
3958
3959 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3960 if (ret_val)
3961 return ret_val;
3962
3963 if (!link) {
3964 DEBUGOUT("Phy info is only valid if link is up\n");
3965 return -E1000_ERR_CONFIG;
3966 }
3967
3968 phy->polarity_correction = TRUE;
3969
3970 ret_val = e1000_check_polarity_82577(hw);
3971 if (ret_val)
3972 return ret_val;
3973
3974 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3975 if (ret_val)
3976 return ret_val;
3977
3978 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3979
3980 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3981 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3982 ret_val = hw->phy.ops.get_cable_length(hw);
3983 if (ret_val)
3984 return ret_val;
3985
3986 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3987 if (ret_val)
3988 return ret_val;
3989
3990 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3991 ? e1000_1000t_rx_status_ok
3992 : e1000_1000t_rx_status_not_ok;
3993
3994 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3995 ? e1000_1000t_rx_status_ok
3996 : e1000_1000t_rx_status_not_ok;
3997 } else {
3998 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3999 phy->local_rx = e1000_1000t_rx_status_undefined;
4000 phy->remote_rx = e1000_1000t_rx_status_undefined;
4001 }
4002
4003 return E1000_SUCCESS;
4004 }
4005
4006 /**
4007 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4008 * @hw: pointer to the HW structure
4009 *
4010 * Reads the diagnostic status register and verifies result is valid before
4011 * placing it in the phy_cable_length field.
4012 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)4013 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4014 {
4015 struct e1000_phy_info *phy = &hw->phy;
4016 s32 ret_val;
4017 u16 phy_data, length;
4018
4019 DEBUGFUNC("e1000_get_cable_length_82577");
4020
4021 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4022 if (ret_val)
4023 return ret_val;
4024
4025 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4026 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4027
4028 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4029 return -E1000_ERR_PHY;
4030
4031 phy->cable_length = length;
4032
4033 return E1000_SUCCESS;
4034 }
4035
4036 /**
4037 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4038 * @hw: pointer to the HW structure
4039 * @offset: register offset to write to
4040 * @data: data to write at register offset
4041 *
4042 * Acquires semaphore, if necessary, then writes the data to PHY register
4043 * at the offset. Release any acquired semaphores before exiting.
4044 **/
e1000_write_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 data)4045 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4046 {
4047 s32 ret_val;
4048 u16 page = offset >> GS40G_PAGE_SHIFT;
4049
4050 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4051
4052 offset = offset & GS40G_OFFSET_MASK;
4053 ret_val = hw->phy.ops.acquire(hw);
4054 if (ret_val)
4055 return ret_val;
4056
4057 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4058 if (ret_val)
4059 goto release;
4060 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4061
4062 release:
4063 hw->phy.ops.release(hw);
4064 return ret_val;
4065 }
4066
4067 /**
4068 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4069 * @hw: pointer to the HW structure
4070 * @offset: lower half is register offset to read to
4071 * upper half is page to use.
4072 * @data: data to read at register offset
4073 *
4074 * Acquires semaphore, if necessary, then reads the data in the PHY register
4075 * at the offset. Release any acquired semaphores before exiting.
4076 **/
e1000_read_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 * data)4077 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4078 {
4079 s32 ret_val;
4080 u16 page = offset >> GS40G_PAGE_SHIFT;
4081
4082 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4083
4084 offset = offset & GS40G_OFFSET_MASK;
4085 ret_val = hw->phy.ops.acquire(hw);
4086 if (ret_val)
4087 return ret_val;
4088
4089 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4090 if (ret_val)
4091 goto release;
4092 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4093
4094 release:
4095 hw->phy.ops.release(hw);
4096 return ret_val;
4097 }
4098
4099 /**
4100 * e1000_read_phy_reg_mphy - Read mPHY control register
4101 * @hw: pointer to the HW structure
4102 * @address: address to be read
4103 * @data: pointer to the read data
4104 *
4105 * Reads the mPHY control register in the PHY at offset and stores the
4106 * information read to data.
4107 **/
e1000_read_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 * data)4108 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4109 {
4110 u32 mphy_ctrl = 0;
4111 bool locked = FALSE;
4112 bool ready;
4113
4114 DEBUGFUNC("e1000_read_phy_reg_mphy");
4115
4116 /* Check if mPHY is ready to read/write operations */
4117 ready = e1000_is_mphy_ready(hw);
4118 if (!ready)
4119 return -E1000_ERR_PHY;
4120
4121 /* Check if mPHY access is disabled and enable it if so */
4122 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4123 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4124 locked = TRUE;
4125 ready = e1000_is_mphy_ready(hw);
4126 if (!ready)
4127 return -E1000_ERR_PHY;
4128 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4129 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4130 }
4131
4132 /* Set the address that we want to read */
4133 ready = e1000_is_mphy_ready(hw);
4134 if (!ready)
4135 return -E1000_ERR_PHY;
4136
4137 /* We mask address, because we want to use only current lane */
4138 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4139 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4140 (address & E1000_MPHY_ADDRESS_MASK);
4141 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4142
4143 /* Read data from the address */
4144 ready = e1000_is_mphy_ready(hw);
4145 if (!ready)
4146 return -E1000_ERR_PHY;
4147 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4148
4149 /* Disable access to mPHY if it was originally disabled */
4150 if (locked)
4151 ready = e1000_is_mphy_ready(hw);
4152 if (!ready)
4153 return -E1000_ERR_PHY;
4154 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4155 E1000_MPHY_DIS_ACCESS);
4156
4157 return E1000_SUCCESS;
4158 }
4159
4160 /**
4161 * e1000_write_phy_reg_mphy - Write mPHY control register
4162 * @hw: pointer to the HW structure
4163 * @address: address to write to
4164 * @data: data to write to register at offset
4165 * @line_override: used when we want to use different line than default one
4166 *
4167 * Writes data to mPHY control register.
4168 **/
e1000_write_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 data,bool line_override)4169 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4170 bool line_override)
4171 {
4172 u32 mphy_ctrl = 0;
4173 bool locked = FALSE;
4174 bool ready;
4175
4176 DEBUGFUNC("e1000_write_phy_reg_mphy");
4177
4178 /* Check if mPHY is ready to read/write operations */
4179 ready = e1000_is_mphy_ready(hw);
4180 if (!ready)
4181 return -E1000_ERR_PHY;
4182
4183 /* Check if mPHY access is disabled and enable it if so */
4184 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4185 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4186 locked = TRUE;
4187 ready = e1000_is_mphy_ready(hw);
4188 if (!ready)
4189 return -E1000_ERR_PHY;
4190 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4191 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4192 }
4193
4194 /* Set the address that we want to read */
4195 ready = e1000_is_mphy_ready(hw);
4196 if (!ready)
4197 return -E1000_ERR_PHY;
4198
4199 /* We mask address, because we want to use only current lane */
4200 if (line_override)
4201 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4202 else
4203 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4204 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4205 (address & E1000_MPHY_ADDRESS_MASK);
4206 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4207
4208 /* Read data from the address */
4209 ready = e1000_is_mphy_ready(hw);
4210 if (!ready)
4211 return -E1000_ERR_PHY;
4212 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4213
4214 /* Disable access to mPHY if it was originally disabled */
4215 if (locked)
4216 ready = e1000_is_mphy_ready(hw);
4217 if (!ready)
4218 return -E1000_ERR_PHY;
4219 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4220 E1000_MPHY_DIS_ACCESS);
4221
4222 return E1000_SUCCESS;
4223 }
4224
4225 /**
4226 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4227 * @hw: pointer to the HW structure
4228 *
4229 * Returns mPHY control register status.
4230 **/
e1000_is_mphy_ready(struct e1000_hw * hw)4231 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4232 {
4233 u16 retry_count = 0;
4234 u32 mphy_ctrl = 0;
4235 bool ready = FALSE;
4236
4237 while (retry_count < 2) {
4238 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4239 if (mphy_ctrl & E1000_MPHY_BUSY) {
4240 usec_delay(20);
4241 retry_count++;
4242 continue;
4243 }
4244 ready = TRUE;
4245 break;
4246 }
4247
4248 if (!ready)
4249 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4250
4251 return ready;
4252 }
4253