1*d39a76e7Sxw161283 /*
2*d39a76e7Sxw161283 * CDDL HEADER START
3*d39a76e7Sxw161283 *
4*d39a76e7Sxw161283 * The contents of this file are subject to the terms of the
5*d39a76e7Sxw161283 * Common Development and Distribution License (the "License").
6*d39a76e7Sxw161283 * You may not use this file except in compliance with the License.
7*d39a76e7Sxw161283 *
8*d39a76e7Sxw161283 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*d39a76e7Sxw161283 * or http://www.opensolaris.org/os/licensing.
10*d39a76e7Sxw161283 * See the License for the specific language governing permissions
11*d39a76e7Sxw161283 * and limitations under the License.
12*d39a76e7Sxw161283 *
13*d39a76e7Sxw161283 * When distributing Covered Code, include this CDDL HEADER in each
14*d39a76e7Sxw161283 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*d39a76e7Sxw161283 * If applicable, add the following below this CDDL HEADER, with the
16*d39a76e7Sxw161283 * fields enclosed by brackets "[]" replaced with your own identifying
17*d39a76e7Sxw161283 * information: Portions Copyright [yyyy] [name of copyright owner]
18*d39a76e7Sxw161283 *
19*d39a76e7Sxw161283 * CDDL HEADER END
20*d39a76e7Sxw161283 */
21*d39a76e7Sxw161283
22*d39a76e7Sxw161283 /*
23*d39a76e7Sxw161283 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
24*d39a76e7Sxw161283 */
25*d39a76e7Sxw161283
26*d39a76e7Sxw161283 #include "common.h"
27*d39a76e7Sxw161283 #include "mv88e1xxx.h"
28*d39a76e7Sxw161283 #include "cphy.h"
29*d39a76e7Sxw161283 #include "elmer0.h"
30*d39a76e7Sxw161283
31*d39a76e7Sxw161283 /* MV88E1XXX MDI crossover register values */
32*d39a76e7Sxw161283 #define CROSSOVER_MDI 0
33*d39a76e7Sxw161283 #define CROSSOVER_MDIX 1
34*d39a76e7Sxw161283 #define CROSSOVER_AUTO 3
35*d39a76e7Sxw161283
36*d39a76e7Sxw161283 #define INTR_ENABLE_MASK 0x6CA0
37*d39a76e7Sxw161283
38*d39a76e7Sxw161283 /*
39*d39a76e7Sxw161283 * Set the bits given by 'bitval' in PHY register 'reg'.
40*d39a76e7Sxw161283 */
mdio_set_bit(struct cphy * cphy,int reg,u32 bitval)41*d39a76e7Sxw161283 static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
42*d39a76e7Sxw161283 {
43*d39a76e7Sxw161283 u32 val;
44*d39a76e7Sxw161283
45*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, reg, &val);
46*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, reg, val | bitval);
47*d39a76e7Sxw161283 }
48*d39a76e7Sxw161283
49*d39a76e7Sxw161283 /*
50*d39a76e7Sxw161283 * Clear the bits given by 'bitval' in PHY register 'reg'.
51*d39a76e7Sxw161283 */
mdio_clear_bit(struct cphy * cphy,int reg,u32 bitval)52*d39a76e7Sxw161283 static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
53*d39a76e7Sxw161283 {
54*d39a76e7Sxw161283 u32 val;
55*d39a76e7Sxw161283
56*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, reg, &val);
57*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, reg, val & ~bitval);
58*d39a76e7Sxw161283 }
59*d39a76e7Sxw161283
60*d39a76e7Sxw161283 /*
61*d39a76e7Sxw161283 * NAME: phy_reset
62*d39a76e7Sxw161283 *
63*d39a76e7Sxw161283 * DESC: Reset the given PHY's port. NOTE: This is not a global
64*d39a76e7Sxw161283 * chip reset.
65*d39a76e7Sxw161283 *
66*d39a76e7Sxw161283 * PARAMS: cphy - Pointer to PHY instance data.
67*d39a76e7Sxw161283 *
68*d39a76e7Sxw161283 * RETURN: 0 - Successfull reset.
69*d39a76e7Sxw161283 * -1 - Timeout.
70*d39a76e7Sxw161283 */
71*d39a76e7Sxw161283 /* ARGSUSED */
mv88e1xxx_reset(struct cphy * cphy,int wait)72*d39a76e7Sxw161283 static int mv88e1xxx_reset(struct cphy *cphy, int wait)
73*d39a76e7Sxw161283 {
74*d39a76e7Sxw161283 u32 ctl;
75*d39a76e7Sxw161283 int time_out = 1000;
76*d39a76e7Sxw161283
77*d39a76e7Sxw161283 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
78*d39a76e7Sxw161283
79*d39a76e7Sxw161283 do {
80*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
81*d39a76e7Sxw161283 ctl &= BMCR_RESET;
82*d39a76e7Sxw161283 if (ctl)
83*d39a76e7Sxw161283 DELAY_US(1);
84*d39a76e7Sxw161283 } while (ctl && --time_out);
85*d39a76e7Sxw161283
86*d39a76e7Sxw161283 return ctl ? -1 : 0;
87*d39a76e7Sxw161283 }
88*d39a76e7Sxw161283
mv88e1xxx_interrupt_enable(struct cphy * cphy)89*d39a76e7Sxw161283 static int mv88e1xxx_interrupt_enable(struct cphy *cphy)
90*d39a76e7Sxw161283 {
91*d39a76e7Sxw161283 /* Enable PHY interrupts. */
92*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER,
93*d39a76e7Sxw161283 INTR_ENABLE_MASK);
94*d39a76e7Sxw161283
95*d39a76e7Sxw161283 /* Enable Marvell interrupts through Elmer0. */
96*d39a76e7Sxw161283 if (t1_is_asic(cphy->adapter)) {
97*d39a76e7Sxw161283 u32 elmer;
98*d39a76e7Sxw161283
99*d39a76e7Sxw161283 (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
100*d39a76e7Sxw161283 elmer |= ELMER0_GP_BIT1;
101*d39a76e7Sxw161283 if (is_T2(cphy->adapter)) {
102*d39a76e7Sxw161283 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
103*d39a76e7Sxw161283 }
104*d39a76e7Sxw161283 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
105*d39a76e7Sxw161283 }
106*d39a76e7Sxw161283 return 0;
107*d39a76e7Sxw161283 }
108*d39a76e7Sxw161283
mv88e1xxx_interrupt_disable(struct cphy * cphy)109*d39a76e7Sxw161283 static int mv88e1xxx_interrupt_disable(struct cphy *cphy)
110*d39a76e7Sxw161283 {
111*d39a76e7Sxw161283 /* Disable all phy interrupts. */
112*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0);
113*d39a76e7Sxw161283
114*d39a76e7Sxw161283 /* Disable Marvell interrupts through Elmer0. */
115*d39a76e7Sxw161283 if (t1_is_asic(cphy->adapter)) {
116*d39a76e7Sxw161283 u32 elmer;
117*d39a76e7Sxw161283
118*d39a76e7Sxw161283 (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
119*d39a76e7Sxw161283 elmer &= ~ELMER0_GP_BIT1;
120*d39a76e7Sxw161283 if (is_T2(cphy->adapter)) {
121*d39a76e7Sxw161283 elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
122*d39a76e7Sxw161283 }
123*d39a76e7Sxw161283 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
124*d39a76e7Sxw161283 }
125*d39a76e7Sxw161283 return 0;
126*d39a76e7Sxw161283 }
127*d39a76e7Sxw161283
mv88e1xxx_interrupt_clear(struct cphy * cphy)128*d39a76e7Sxw161283 static int mv88e1xxx_interrupt_clear(struct cphy *cphy)
129*d39a76e7Sxw161283 {
130*d39a76e7Sxw161283 u32 elmer;
131*d39a76e7Sxw161283
132*d39a76e7Sxw161283 /* Clear PHY interrupts by reading the register. */
133*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer);
134*d39a76e7Sxw161283
135*d39a76e7Sxw161283 /* Clear Marvell interrupts through Elmer0. */
136*d39a76e7Sxw161283 if (t1_is_asic(cphy->adapter)) {
137*d39a76e7Sxw161283 (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
138*d39a76e7Sxw161283 elmer |= ELMER0_GP_BIT1;
139*d39a76e7Sxw161283 if (is_T2(cphy->adapter)) {
140*d39a76e7Sxw161283 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
141*d39a76e7Sxw161283 }
142*d39a76e7Sxw161283 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
143*d39a76e7Sxw161283 }
144*d39a76e7Sxw161283 return 0;
145*d39a76e7Sxw161283 }
146*d39a76e7Sxw161283
147*d39a76e7Sxw161283 /*
148*d39a76e7Sxw161283 * Set the PHY speed and duplex. This also disables auto-negotiation, except
149*d39a76e7Sxw161283 * for 1Gb/s, where auto-negotiation is mandatory.
150*d39a76e7Sxw161283 */
mv88e1xxx_set_speed_duplex(struct cphy * phy,int speed,int duplex)151*d39a76e7Sxw161283 static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)
152*d39a76e7Sxw161283 {
153*d39a76e7Sxw161283 u32 ctl;
154*d39a76e7Sxw161283
155*d39a76e7Sxw161283 (void) simple_mdio_read(phy, MII_BMCR, &ctl);
156*d39a76e7Sxw161283 if (speed >= 0) {
157*d39a76e7Sxw161283 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
158*d39a76e7Sxw161283 if (speed == SPEED_100)
159*d39a76e7Sxw161283 ctl |= BMCR_SPEED100;
160*d39a76e7Sxw161283 else if (speed == SPEED_1000)
161*d39a76e7Sxw161283 ctl |= BMCR_SPEED1000;
162*d39a76e7Sxw161283 }
163*d39a76e7Sxw161283 if (duplex >= 0) {
164*d39a76e7Sxw161283 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
165*d39a76e7Sxw161283 if (duplex == DUPLEX_FULL)
166*d39a76e7Sxw161283 ctl |= BMCR_FULLDPLX;
167*d39a76e7Sxw161283 }
168*d39a76e7Sxw161283 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */
169*d39a76e7Sxw161283 ctl |= BMCR_ANENABLE;
170*d39a76e7Sxw161283 (void) simple_mdio_write(phy, MII_BMCR, ctl);
171*d39a76e7Sxw161283 return 0;
172*d39a76e7Sxw161283 }
173*d39a76e7Sxw161283
mv88e1xxx_crossover_set(struct cphy * cphy,int crossover)174*d39a76e7Sxw161283 static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
175*d39a76e7Sxw161283 {
176*d39a76e7Sxw161283 u32 data32;
177*d39a76e7Sxw161283
178*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32);
179*d39a76e7Sxw161283 data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE);
180*d39a76e7Sxw161283 data32 |= V_PSCR_MDI_XOVER_MODE(crossover);
181*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32);
182*d39a76e7Sxw161283 return 0;
183*d39a76e7Sxw161283 }
184*d39a76e7Sxw161283
mv88e1xxx_autoneg_enable(struct cphy * cphy)185*d39a76e7Sxw161283 static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
186*d39a76e7Sxw161283 {
187*d39a76e7Sxw161283 u32 ctl;
188*d39a76e7Sxw161283
189*d39a76e7Sxw161283 (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
190*d39a76e7Sxw161283
191*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
192*d39a76e7Sxw161283 /* restart autoneg for change to take effect */
193*d39a76e7Sxw161283 ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
194*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MII_BMCR, ctl);
195*d39a76e7Sxw161283 return 0;
196*d39a76e7Sxw161283 }
197*d39a76e7Sxw161283
mv88e1xxx_autoneg_disable(struct cphy * cphy)198*d39a76e7Sxw161283 static int mv88e1xxx_autoneg_disable(struct cphy *cphy)
199*d39a76e7Sxw161283 {
200*d39a76e7Sxw161283 u32 ctl;
201*d39a76e7Sxw161283
202*d39a76e7Sxw161283 /*
203*d39a76e7Sxw161283 * Crossover *must* be set to manual in order to disable auto-neg.
204*d39a76e7Sxw161283 * The Alaska FAQs document highlights this point.
205*d39a76e7Sxw161283 */
206*d39a76e7Sxw161283 (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI);
207*d39a76e7Sxw161283
208*d39a76e7Sxw161283 /*
209*d39a76e7Sxw161283 * Must include autoneg reset when disabling auto-neg. This
210*d39a76e7Sxw161283 * is described in the Alaska FAQ document.
211*d39a76e7Sxw161283 */
212*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
213*d39a76e7Sxw161283 ctl &= ~BMCR_ANENABLE;
214*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
215*d39a76e7Sxw161283 return 0;
216*d39a76e7Sxw161283 }
217*d39a76e7Sxw161283
mv88e1xxx_autoneg_restart(struct cphy * cphy)218*d39a76e7Sxw161283 static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
219*d39a76e7Sxw161283 {
220*d39a76e7Sxw161283 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
221*d39a76e7Sxw161283 return 0;
222*d39a76e7Sxw161283 }
223*d39a76e7Sxw161283
mv88e1xxx_advertise(struct cphy * phy,unsigned int advertise_map)224*d39a76e7Sxw161283 static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map)
225*d39a76e7Sxw161283 {
226*d39a76e7Sxw161283 u32 val = 0;
227*d39a76e7Sxw161283
228*d39a76e7Sxw161283 if (advertise_map &
229*d39a76e7Sxw161283 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
230*d39a76e7Sxw161283 (void) simple_mdio_read(phy, MII_GBCR, &val);
231*d39a76e7Sxw161283 val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL);
232*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_1000baseT_Half)
233*d39a76e7Sxw161283 val |= GBCR_ADV_1000HALF;
234*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_1000baseT_Full)
235*d39a76e7Sxw161283 val |= GBCR_ADV_1000FULL;
236*d39a76e7Sxw161283 }
237*d39a76e7Sxw161283 (void) simple_mdio_write(phy, MII_GBCR, val);
238*d39a76e7Sxw161283
239*d39a76e7Sxw161283 val = 1;
240*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_10baseT_Half)
241*d39a76e7Sxw161283 val |= ADVERTISE_10HALF;
242*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_10baseT_Full)
243*d39a76e7Sxw161283 val |= ADVERTISE_10FULL;
244*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_100baseT_Half)
245*d39a76e7Sxw161283 val |= ADVERTISE_100HALF;
246*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_100baseT_Full)
247*d39a76e7Sxw161283 val |= ADVERTISE_100FULL;
248*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_PAUSE)
249*d39a76e7Sxw161283 val |= ADVERTISE_PAUSE;
250*d39a76e7Sxw161283 if (advertise_map & ADVERTISED_ASYM_PAUSE)
251*d39a76e7Sxw161283 val |= ADVERTISE_PAUSE_ASYM;
252*d39a76e7Sxw161283 (void) simple_mdio_write(phy, MII_ADVERTISE, val);
253*d39a76e7Sxw161283 return 0;
254*d39a76e7Sxw161283 }
255*d39a76e7Sxw161283
mv88e1xxx_set_loopback(struct cphy * cphy,int on)256*d39a76e7Sxw161283 static int mv88e1xxx_set_loopback(struct cphy *cphy, int on)
257*d39a76e7Sxw161283 {
258*d39a76e7Sxw161283 if (on)
259*d39a76e7Sxw161283 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
260*d39a76e7Sxw161283 else
261*d39a76e7Sxw161283 mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
262*d39a76e7Sxw161283 return 0;
263*d39a76e7Sxw161283 }
264*d39a76e7Sxw161283
mv88e1xxx_get_link_status(struct cphy * cphy,int * link_ok,int * speed,int * duplex,int * fc)265*d39a76e7Sxw161283 static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
266*d39a76e7Sxw161283 int *speed, int *duplex, int *fc)
267*d39a76e7Sxw161283 {
268*d39a76e7Sxw161283 u32 status;
269*d39a76e7Sxw161283 int sp = -1, dplx = -1, pause = 0;
270*d39a76e7Sxw161283
271*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
272*d39a76e7Sxw161283 if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
273*d39a76e7Sxw161283 if (status & V_PSSR_RX_PAUSE)
274*d39a76e7Sxw161283 pause |= PAUSE_RX;
275*d39a76e7Sxw161283 if (status & V_PSSR_TX_PAUSE)
276*d39a76e7Sxw161283 pause |= PAUSE_TX;
277*d39a76e7Sxw161283 dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
278*d39a76e7Sxw161283 sp = G_PSSR_SPEED(status);
279*d39a76e7Sxw161283 if (sp == 0)
280*d39a76e7Sxw161283 sp = SPEED_10;
281*d39a76e7Sxw161283 else if (sp == 1)
282*d39a76e7Sxw161283 sp = SPEED_100;
283*d39a76e7Sxw161283 else
284*d39a76e7Sxw161283 sp = SPEED_1000;
285*d39a76e7Sxw161283 }
286*d39a76e7Sxw161283 if (link_ok)
287*d39a76e7Sxw161283 *link_ok = (status & V_PSSR_LINK) != 0;
288*d39a76e7Sxw161283 if (speed)
289*d39a76e7Sxw161283 *speed = sp;
290*d39a76e7Sxw161283 if (duplex)
291*d39a76e7Sxw161283 *duplex = dplx;
292*d39a76e7Sxw161283 if (fc)
293*d39a76e7Sxw161283 *fc = pause;
294*d39a76e7Sxw161283 return 0;
295*d39a76e7Sxw161283 }
296*d39a76e7Sxw161283
mv88e1xxx_downshift_set(struct cphy * cphy,int downshift_enable)297*d39a76e7Sxw161283 static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
298*d39a76e7Sxw161283 {
299*d39a76e7Sxw161283 u32 val;
300*d39a76e7Sxw161283
301*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val);
302*d39a76e7Sxw161283
303*d39a76e7Sxw161283 /*
304*d39a76e7Sxw161283 * Set the downshift counter to 2 so we try to establish Gb link
305*d39a76e7Sxw161283 * twice before downshifting.
306*d39a76e7Sxw161283 */
307*d39a76e7Sxw161283 val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT));
308*d39a76e7Sxw161283
309*d39a76e7Sxw161283 if (downshift_enable)
310*d39a76e7Sxw161283 val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2);
311*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val);
312*d39a76e7Sxw161283 return 0;
313*d39a76e7Sxw161283 }
314*d39a76e7Sxw161283
mv88e1xxx_interrupt_handler(struct cphy * cphy)315*d39a76e7Sxw161283 static int mv88e1xxx_interrupt_handler(struct cphy *cphy)
316*d39a76e7Sxw161283 {
317*d39a76e7Sxw161283 int cphy_cause = 0;
318*d39a76e7Sxw161283 u32 status;
319*d39a76e7Sxw161283
320*d39a76e7Sxw161283 /*
321*d39a76e7Sxw161283 * Loop until cause reads zero. Need to handle bouncing interrupts.
322*d39a76e7Sxw161283 */
323*d39a76e7Sxw161283 /*CONSTCOND*/
324*d39a76e7Sxw161283 while (1) {
325*d39a76e7Sxw161283 u32 cause;
326*d39a76e7Sxw161283
327*d39a76e7Sxw161283 (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER,
328*d39a76e7Sxw161283 &cause);
329*d39a76e7Sxw161283 cause &= INTR_ENABLE_MASK;
330*d39a76e7Sxw161283 if (!cause) break;
331*d39a76e7Sxw161283
332*d39a76e7Sxw161283 if (cause & MV88E1XXX_INTR_LINK_CHNG) {
333*d39a76e7Sxw161283 (void) simple_mdio_read(cphy,
334*d39a76e7Sxw161283 MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
335*d39a76e7Sxw161283
336*d39a76e7Sxw161283 if (status & MV88E1XXX_INTR_LINK_CHNG) {
337*d39a76e7Sxw161283 cphy->state |= PHY_LINK_UP;
338*d39a76e7Sxw161283 } else {
339*d39a76e7Sxw161283 cphy->state &= ~PHY_LINK_UP;
340*d39a76e7Sxw161283 if (cphy->state & PHY_AUTONEG_EN)
341*d39a76e7Sxw161283 cphy->state &= ~PHY_AUTONEG_RDY;
342*d39a76e7Sxw161283 cphy_cause |= cphy_cause_link_change;
343*d39a76e7Sxw161283 }
344*d39a76e7Sxw161283 }
345*d39a76e7Sxw161283
346*d39a76e7Sxw161283 if (cause & MV88E1XXX_INTR_AUTONEG_DONE)
347*d39a76e7Sxw161283 cphy->state |= PHY_AUTONEG_RDY;
348*d39a76e7Sxw161283
349*d39a76e7Sxw161283 if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) ==
350*d39a76e7Sxw161283 (PHY_LINK_UP | PHY_AUTONEG_RDY))
351*d39a76e7Sxw161283 cphy_cause |= cphy_cause_link_change;
352*d39a76e7Sxw161283 }
353*d39a76e7Sxw161283 return cphy_cause;
354*d39a76e7Sxw161283 }
355*d39a76e7Sxw161283
mv88e1xxx_destroy(struct cphy * cphy)356*d39a76e7Sxw161283 static void mv88e1xxx_destroy(struct cphy *cphy)
357*d39a76e7Sxw161283 {
358*d39a76e7Sxw161283 t1_os_free((void *)cphy, sizeof(*cphy));
359*d39a76e7Sxw161283 }
360*d39a76e7Sxw161283
361*d39a76e7Sxw161283 #ifdef C99_NOT_SUPPORTED
362*d39a76e7Sxw161283 static struct cphy_ops mv88e1xxx_ops = {
363*d39a76e7Sxw161283 mv88e1xxx_destroy,
364*d39a76e7Sxw161283 mv88e1xxx_reset,
365*d39a76e7Sxw161283 mv88e1xxx_interrupt_enable,
366*d39a76e7Sxw161283 mv88e1xxx_interrupt_disable,
367*d39a76e7Sxw161283 mv88e1xxx_interrupt_clear,
368*d39a76e7Sxw161283 mv88e1xxx_interrupt_handler,
369*d39a76e7Sxw161283 mv88e1xxx_autoneg_enable,
370*d39a76e7Sxw161283 mv88e1xxx_autoneg_disable,
371*d39a76e7Sxw161283 mv88e1xxx_autoneg_restart,
372*d39a76e7Sxw161283 mv88e1xxx_advertise,
373*d39a76e7Sxw161283 mv88e1xxx_set_loopback,
374*d39a76e7Sxw161283 mv88e1xxx_set_speed_duplex,
375*d39a76e7Sxw161283 mv88e1xxx_get_link_status,
376*d39a76e7Sxw161283 };
377*d39a76e7Sxw161283 #else
378*d39a76e7Sxw161283 static struct cphy_ops mv88e1xxx_ops = {
379*d39a76e7Sxw161283 .destroy = mv88e1xxx_destroy,
380*d39a76e7Sxw161283 .reset = mv88e1xxx_reset,
381*d39a76e7Sxw161283 .interrupt_enable = mv88e1xxx_interrupt_enable,
382*d39a76e7Sxw161283 .interrupt_disable = mv88e1xxx_interrupt_disable,
383*d39a76e7Sxw161283 .interrupt_clear = mv88e1xxx_interrupt_clear,
384*d39a76e7Sxw161283 .interrupt_handler = mv88e1xxx_interrupt_handler,
385*d39a76e7Sxw161283 .autoneg_enable = mv88e1xxx_autoneg_enable,
386*d39a76e7Sxw161283 .autoneg_disable = mv88e1xxx_autoneg_disable,
387*d39a76e7Sxw161283 .autoneg_restart = mv88e1xxx_autoneg_restart,
388*d39a76e7Sxw161283 .advertise = mv88e1xxx_advertise,
389*d39a76e7Sxw161283 .set_loopback = mv88e1xxx_set_loopback,
390*d39a76e7Sxw161283 .set_speed_duplex = mv88e1xxx_set_speed_duplex,
391*d39a76e7Sxw161283 .get_link_status = mv88e1xxx_get_link_status,
392*d39a76e7Sxw161283 };
393*d39a76e7Sxw161283 #endif
394*d39a76e7Sxw161283
mv88e1xxx_phy_create(adapter_t * adapter,int phy_addr,struct mdio_ops * mdio_ops)395*d39a76e7Sxw161283 static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr,
396*d39a76e7Sxw161283 struct mdio_ops *mdio_ops)
397*d39a76e7Sxw161283 {
398*d39a76e7Sxw161283 struct cphy *cphy = t1_os_malloc_wait_zero(sizeof(*cphy));
399*d39a76e7Sxw161283
400*d39a76e7Sxw161283 if (!cphy) return NULL;
401*d39a76e7Sxw161283
402*d39a76e7Sxw161283 cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops);
403*d39a76e7Sxw161283
404*d39a76e7Sxw161283 /* Configure particular PHY's to run in a different mode. */
405*d39a76e7Sxw161283 if ((board_info(adapter)->caps & SUPPORTED_TP) &&
406*d39a76e7Sxw161283 board_info(adapter)->chip_phy == CHBT_PHY_88E1111) {
407*d39a76e7Sxw161283 /*
408*d39a76e7Sxw161283 * Configure the PHY transmitter as class A to reduce EMI.
409*d39a76e7Sxw161283 */
410*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB);
411*d39a76e7Sxw161283 (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_REGISTER, 0x8004);
412*d39a76e7Sxw161283 }
413*d39a76e7Sxw161283 (void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */
414*d39a76e7Sxw161283
415*d39a76e7Sxw161283 /* LED */
416*d39a76e7Sxw161283 if (is_T2(adapter)) {
417*d39a76e7Sxw161283 (void) simple_mdio_write(cphy,
418*d39a76e7Sxw161283 MV88E1XXX_LED_CONTROL_REGISTER, 0x1);
419*d39a76e7Sxw161283 }
420*d39a76e7Sxw161283
421*d39a76e7Sxw161283 return cphy;
422*d39a76e7Sxw161283 }
423*d39a76e7Sxw161283
424*d39a76e7Sxw161283 /* ARGSUSED */
mv88e1xxx_phy_reset(adapter_t * adapter)425*d39a76e7Sxw161283 static int mv88e1xxx_phy_reset(adapter_t* adapter)
426*d39a76e7Sxw161283 {
427*d39a76e7Sxw161283 return 0;
428*d39a76e7Sxw161283 }
429*d39a76e7Sxw161283
430*d39a76e7Sxw161283 struct gphy t1_mv88e1xxx_ops = {
431*d39a76e7Sxw161283 mv88e1xxx_phy_create,
432*d39a76e7Sxw161283 mv88e1xxx_phy_reset
433*d39a76e7Sxw161283 };
434