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/illumos-gate/usr/src/lib/libc/sparc/sys/
H A Dvforkx.S82 ld [%g7 + UL_SIGMASK], %o1
83 ld [%g7 + UL_SIGMASK + 4], %o2
84 ld [%g7 + UL_SIGMASK + 8], %o3
85 ld [%g7 + UL_SIGMASK + 12], %o4
100 ld [%g7 + UL_VFORK], %g1
108 st %g1, [%g7 + UL_VFORK]
113 stn %g0, [%g7 + UL_SCHEDCTL]
114 stn %g0, [%g7 + UL_SCHEDCTL_CALLED]
118 ld [%g7 + UL_SIGMASK], %o1
119 ld [%g7 + UL_SIGMASK + 4], %o2
[all …]
/illumos-gate/usr/src/uts/sfmmu/ml/
H A Dsfmmu_asm.S59 rd %pc, %g7
1700 rdpr %tt, %g7
1710 wrpr %g7, %tt
1749 rdpr %tt, %g7
1750 cmp %g7, FAST_IMMU_MISS_TT
1753 cmp %g7, T_INSTR_MMU_MISS
1757 cmp %g7, FAST_DMMU_MISS_TT
1759 cmp %g7, T_DATA_MMU_MISS
2260 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2267 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
[all …]
H A Dsfmmu_kdi.S265 jmpl %g3, %g7 /* => %g1: TTE or 0 */
266 add %g7, 8, %g7
325 6: jmp %g7
/illumos-gate/usr/src/uts/sun4u/ml/
H A Dwbuf.S155 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
162 add %g5, 1, %g7
163 st %g7, [%g6 + MPCB_WBCNT]
167 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
168 add %g6, %g7, %g7
169 stn %sp, [%g7 + MPCB_SPBUF]
170 sll %g5, RWIN32SHIFT, %g7
172 add %g5, %g7, %g7
173 SAVE_V8WINDOW(%g7)
289 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
[all …]
H A Dtrap_table.S91 rd %pc, %g7
777 mov WSTATE_USER32, %g7 ;\
808 mov WSTATE_USER64, %g7 ;\
1071 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1073 cmp %g4, %g7 ;\
1106 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1110 cmp %g4, %g7 ;\
1162 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1164 cmp %g4, %g7 ;\
1199 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
[all …]
/illumos-gate/usr/src/uts/sun4v/ml/
H A Dwbuf.S157 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
165 add %g5, 1, %g7
166 sta %g7, [%g6 + MPCB_WBCNT]%asi
170 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
171 add %g6, %g7, %g7
172 stna %sp, [%g7 + MPCB_SPBUF]%asi
173 sll %g5, RWIN32SHIFT, %g7
175 add %g5, %g7, %g7
176 SAVE_V8WINDOW_ASI(%g7)
350 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
[all …]
H A Dmach_interrupt.S59 ! %g7 tail ptr
63 ldxa [%g4]ASI_QUEUE, %g7 ! %g7 = tail ptr
64 cmp %g6, %g7
481 set CPU_NRQ_SIZE, %g7
482 add %g4, %g7, %g7 ! %g7 = PA of ER in kernel buf
484 ldxa [%g7]ASI_MEM, %g5 ! %g5 = first 8 byte of ER buf
492 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 0 - 7
495 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 8 - 15
498 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 16 - 23
501 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 24 - 31
[all …]
H A Dtrap_table.S92 rd %pc, %g7
657 mov WSTATE_USER32, %g7 ;\
688 mov WSTATE_USER64, %g7 ;\
934 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
941 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
978 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
985 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1414 or %g2, %g0, %g7
1477 or %g0, %g0, %g7
1534 mov %g7, %l3 ! arg2 == misaligned address
[all …]
/illumos-gate/usr/src/stand/lib/sa/sparc/
H A D_setjmp.S113 set nwindows, %g7
114 ld [%g7], %g7
115 sub %g7, 2, %g6
120 sub %g7, 2, %g6
/illumos-gate/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu_asm.S96 mov MMU_PCONTEXT, %g7
102 ldxa [%g7]ASI_MMU_CTX, %g5 /* %g5 = pri-ctx */
107 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
114 mov %o5, %g7
129 mov %g7, %o5
149 mov MMU_PCONTEXT, %g7
155 ldxa [%g7]ASI_MMU_CTX, %g4 /* %g4 = pri-ctx */
159 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
166 mov %o5, %g7
175 mov %g7, %o5
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus_asm.S191 ldxa [%g0]ASI_ESTATE_ERR, %g7
192 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
218 stxa %g7, [%g0]ASI_ESTATE_ERR
294 rd %asi, %g7
308 wr %g0, %g7, %asi
314 wr %g0, %g7, %asi
320 wr %g0, %g7, %asi
751 mov %g2, %g7 ! Next we get the DTLB_1 index
755 PN_GET_TLB_INDEX(%g7, %g5) ! %g7 has the DTLB_1 index
756 sllx %g7, PN_TLB_ACC_IDX_SHIFT, %g7 ! shift the index into place
[all …]
H A Dus3_cheetah_asm.S120 ldxa [%g0]ASI_ESTATE_ERR, %g7
121 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
146 stxa %g7, [%g0]ASI_ESTATE_ERR
215 rd %asi, %g7
229 wr %g0, %g7, %asi
235 wr %g0, %g7, %asi
241 wr %g0, %g7, %asi
H A Dus3_jalapeno_asm.S409 JP_FORCE_FULL_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
412 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
415 JP_RESTORE_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
428 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
435 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_4);
443 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
542 ldxa [%g0]ASI_ESTATE_ERR, %g7
543 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
574 stxa %g7, [%g0]ASI_ESTATE_ERR
643 rd %asi, %g7
[all …]
H A Dus3_common_asm.S1065 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
1073 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
1080 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_5);
1088 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1338 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, ce_err_1);
1346 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1541 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, async_err_1);
1549 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1561 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
1569 UNPARK_SIBLING_CORE(%g1, %g5, %g7)
[all …]
/illumos-gate/usr/src/test/util-tests/tests/dis/sparc/
H A Dtst.regs.s30 add %g5, %g6, %g7
31 add %g6, %g7, %o0
32 add %g7, %o0, %o1
H A Dtst.regs.out6 libdis_test+0x14: 8e 01 40 06 add %g5, %g6, %g7
7 libdis_test+0x18: 90 01 80 07 add %g6, %g7, %o0
8 libdis_test+0x1c: 92 01 c0 08 add %g7, %o0, %o1
/illumos-gate/usr/src/lib/libc/sparc/gen/
H A D_stack_grow.S64 ldn [%g7 + UL_USTACK + SS_SP], %o1
65 ldn [%g7 + UL_USTACK + SS_SIZE], %o2
H A Dsmt_pause.S50 ld [%g7 + UL_LWPID], %i5
/illumos-gate/usr/src/lib/libc/sparc/threads/
H A Dtls_get_addr.S71 ldn [%g7 + UL_TLSENT], %o2
72 ldn [%g7 + UL_NTLSENT], %o3
H A Dasm_subr.S53 mov %o0, %g7
71 stn %g7, [%o0 + 6*GREGSIZE]
/illumos-gate/usr/src/lib/libm/common/C/
H A D__lgamma.c71 g7 = 4.974607845568932035012064e0, variable
243 p = g0+y*(g1+y*(g2+y*(g3+y*(g4+y*(g5+y*(g6+y*g7)))))); in __k_lgamma()
252 p = g0+y*(g1+y*(g2+y*(g3+y*(g4+y*(g5+y*(g6+y*g7)))))); in __k_lgamma()
/illumos-gate/usr/src/uts/sun4/ml/
H A Dinterrupt.S51 ! %g3, %g5, %g6, %g7 - temps
70 lduh [%g2 + IV_FLAGS], %g7 ! %g7 = iv->iv_flags
71 and %g7, IV_SOFTINT_MT, %g3 ! %g3 = iv->iv_flags & IV_SOFTINT_MT
73 add %g2, IV_PIL_NEXT, %g7 ! g7% = &iv->iv_pil_next
76 add %g7, %g3, %g7 ! %g5 = &iv->iv_xpil_next[cpuid]
78 ldn [%g7], %g3 ! %g3 = next intr_vec_t
117 stn %g0, [%g7] ! clear iv->iv_pil_next or
1505 ! %g3,%g5-g7 - temps
1519 sll %g2, CPTRSHIFT, %g7 ! %g7 = offset to pil entry
1521 ldn [%g6 + %g7], %g5 ! %g5 = cpu->m_cpu.intr_tail[pil]
[all …]
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu_asm.S108 mov MMU_PCONTEXT, %g7
114 ldxa [%g7]ASI_MMU_CTX, %g3 /* get pgz | pri-ctx */
122 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
/illumos-gate/usr/src/lib/libc/sparcv9/gen/
H A Dsmt_pause.S45 ld [%g7 + UL_LWPID], %i3 ! curthread->ul_lwpid
/illumos-gate/usr/src/lib/libc/sparc/unwind/
H A Dunwind_frame.S60 stn %o7, [%g7 + UL_UNWIND_RET] ! save caller's return address

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