Lines Matching refs:g7
59 rd %pc, %g7
1700 rdpr %tt, %g7
1710 wrpr %g7, %tt
1749 rdpr %tt, %g7
1750 cmp %g7, FAST_IMMU_MISS_TT
1753 cmp %g7, T_INSTR_MMU_MISS
1757 cmp %g7, FAST_DMMU_MISS_TT
1759 cmp %g7, T_DATA_MMU_MISS
2260 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2267 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
2270 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2277 GET_TSBE_POINTER(MMU_PAGESHIFT4M, %g3, %g7, %g6, %g5)
2280 CPU_TSBMISS_AREA(%g6, %g7)
2281 HAT_PERCPU_STAT16(%g6, TSBMISS_KPROTS, %g7)
2318 mov %g2, %g7
2319 GET_2ND_TSBE_PTR(%g7, %g1, %g3, %g4, %g5, sfmmu_uprot)
2321 mov %g1, %g7
2322 GET_1ST_TSBE_PTR(%g7, %g1, %g5, sfmmu_uprot)
2326 CPU_TSBMISS_AREA(%g6, %g7)
2327 HAT_PERCPU_STAT16(%g6, TSBMISS_UPROTS, %g7)
2358 cmp %g4, %g7
2377 cmp %g4, %g7
2419 RUNTIME_PATCH_SETX(%g7, %g6)
2430 ldda [%g7 + %g1]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2434 add %g7, %g1, %g1 /* form tsb ptr */
2467 RUNTIME_PATCH_SETX(%g7, %g6)
2478 ldda [%g7 + %g3]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2484 add %g7, %g3, %g3 ! %g3 = kernel second TSB ptr
2532 PROBE_1ST_ITSB(%g1, %g7, uitlb_fast_8k_probefail)
2551 PROBE_1ST_DTSB(%g1, %g7, udtlb_fast_8k_probefail)
2576 PROBE_1ST_ITSB(%g1, %g7, uitlb_8k_probefail)
2581 srlx %g2, TAG_VALO_SHIFT, %g7
2582 PROBE_2ND_ITSB(%g3, %g7)
2620 PROBE_4TH_ITSB(%g6, %g7, uitlb_4m_scd_probefail)
2626 PROBE_2ND_ITSB(%g3, %g7, uitlb_4m_probefail)
2632 PROBE_3RD_ITSB(%g6, %g7, uitlb_8K_scd_probefail)
2639 PROBE_1ST_ITSB(%g1, %g7, uitlb_8k_probefail)
2641 mov %g3, %g7 /* copy tsb8k reg in %g7 */
2642 GET_2ND_TSBE_PTR(%g6, %g7, %g3, %g4, %g5, sfmmu_uitlb)
2644 srlx %g2, TAG_VALO_SHIFT, %g7
2645 PROBE_2ND_ITSB(%g3, %g7, isynth)
2686 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail)
2696 PROBE_4TH_DTSB(%g6, %g7, udtlb_4m_shctx_probefail)
2706 PROBE_3RD_DTSB(%g6, %g7, udtlb_8k_shctx_probefail)
2734 PROBE_4TH_DTSB(%g6, %g7, udtlb_4m_shctx_probefail2)
2744 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail2)
2747 PROBE_1ST_DTSB(%g1, %g7, udtlb_8k_first_probefail2)
2756 PROBE_3RD_DTSB(%g6, %g7, udtlb_8k_shctx_probefail2)
2780 PROBE_1ST_DTSB(%g1, %g7, udtlb_first_probefail)
2793 PROBE_1ST_DTSB(%g1, %g7, udtlb_first_probefail)
2821 mov %g3, %g7
2822 GET_2ND_TSBE_PTR(%g2, %g7, %g3, %g4, %g5, sfmmu_udtlb)
2828 srlx %g2, TAG_VALO_SHIFT, %g7
2829 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail)
2856 rdpr %tl, %g7
2857 cmp %g7, 1
2860 rdpr %tpc, %g7
2862 cmp %g7, %g6
2867 add %g7, RUNTIME_PATCH, %g7 /* must match TSTAT_TSBMISS_INSTR */
2868 wrpr %g7, %tpc
2869 add %g7, 4, %g7
2870 wrpr %g7, %tnpc
2872 CPU_TSBMISS_AREA(%g6, %g7)
2878 ldn [%g6 + TSBMISS_KHATID], %g7
2880 ldn [%g6 + TSBMISS_UHATID], %g7 /* g7 = hatid */
2886 stn %g7, [%g6 + (TSBMISS_SCRATCH + TSBMISS_HATID)]
2889 ldub [%g6 + TSBMISS_URTTEFLAGS], %g7 /* clear ctx1 flag set from */
2890 andn %g7, HAT_CHKCTX1_FLAG, %g7 /* the previous tsb miss */
2891 stub %g7, [%g6 + TSBMISS_URTTEFLAGS]
2894 ISM_CHECK(%g2, %g6, %g3, %g4, %g5, %g7, %g1, tsb_l1, tsb_ism)
2903 ldn [%g6 + (TSBMISS_SCRATCH + TSBMISS_HATID)], %g7
2912 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2941 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2958 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2979 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2997 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3012 rdpr %tt, %g7
3028 ldx [%g6 + TSBMISS_SHARED_UHATID], %g7 /* g7 = srdp */
3029 brz,pn %g7, tsb_pagefault
3032 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3047 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3061 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3076 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3091 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3099 rdpr %tt, %g7
3114 SAVE_CTX1(%g7, %g2, %g1, tsb_shmel)
3128 cmp %g7, FAST_PROT_TT
3132 TTE_SET_REFMOD_ML(%g3, %g4, %g6, %g7, %g5, tsb_lset_refmod,
3135 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
3137 MMU_FAULT_STATUS_AREA(%g7)
3138 ldx [%g7 + MMFSA_D_ADDR], %g5 /* load fault addr for later */
3150 cmp %g7, T_INSTR_MMU_MISS
3153 cmp %g7, FAST_IMMU_MISS_TT
3164 TTE_SET_REF_ML(%g3, %g4, %g6, %g7, %g5, tsb_lset_ref)
3172 rdpr %tt, %g7
3175 cmp %g7, T_INSTR_MMU_MISS
3178 cmp %g7, FAST_IMMU_MISS_TT
3183 ldx [%g2 + MMFSA_CTX_], %g7
3184 sllx %g7, TTARGET_CTX_SHIFT, %g7
3188 or %g2, %g7, %g2
3191 cmp %g7, FAST_IMMU_MISS_TT
3202 srlx %g2, TTARGET_CTX_SHIFT, %g7
3203 brz,pn %g7, tsb_kernel
3205 and %g3, TTE_SZ_BITS, %g7 ! assumes TTE_SZ_SHFT is 0
3207 srlx %g3, TTE_SZ_SHFT, %g7
3212 cmp %g7, TTE4M
3216 cmp %g7, TTESZ_VALID | TTE4M
3218 srlx %g3, TTE_SZ2_SHFT, %g7
3219 andcc %g7, TTE_SZ2_BITS, %g7 ! check 32/256MB
3231 ldub [%g6 + TSBMISS_URTTEFLAGS], %g7
3232 and %g7, HAT_CHKCTX1_FLAG, %g1
3238 GET_3RD_TSBE_PTR(%g5, %g1, %g6, %g7)
3245 mov ASI_N, %g7 ! user TSBs accessed by VA
3246 mov %g7, %asi
3249 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l3)
3271 ldub [%g6 + TSBMISS_URTTEFLAGS], %g7
3272 and %g7, HAT_CHKCTX1_FLAG, %g1
3278 GET_4TH_TSBE_PTR(%g5, %g1, %g6, %g7)
3288 mov ASI_N, %g7 ! user TSBs accessed by VA
3289 mov %g7, %asi
3292 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l4)
3341 mov MMU_TAG_ACCESS, %g7
3342 ldxa [%g7]ASI_DMMU, %g6 /* get tag access va */
3343 GET_4M_PFN_OFF(%g3, %g6, %g5, %g7, 1) /* make 4M pfn offset */
3345 mov ASI_N, %g7 /* user TSBs always accessed by VA */
3346 mov %g7, %asi
3347 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l5) /* update TSB */
3355 mov MMU_TAG_ACCESS, %g7
3356 ldxa [%g7]ASI_IMMU, %g6 /* get tag access va */
3357 GET_4M_PFN_OFF(%g3, %g6, %g5, %g7, 2) /* make 4M pfn offset */
3361 mov ASI_N, %g7 /* user TSBs always accessed by VA */
3362 mov %g7, %asi
3363 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l6) /* update TSB */
3365 SET_TTE4M_PN(%g5, %g7) /* add TTE4M pagesize to TTE */
3373 cmp %g7, TTE4M
3376 cmp %g7, TTESZ_VALID | TTE4M ! no 32M or 256M support
3393 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l7)
3422 ldna [%g4]ASI_MEM, %g7 /* g7 = ism hatid */
3423 brz,a,pn %g7, ptl1_panic /* if zero jmp ahead */
3473 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT32M,
3480 rdpr %tt, %g7
3492 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT256M,
3498 rdpr %tt, %g7
3504 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT4M,
3511 rdpr %tt, %g7
3518 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT64K,
3525 rdpr %tt, %g7
3528 rdpr %tt, %g7
3529 cmp %g7, FAST_PROT_TT
3547 cmp %g7, FAST_IMMU_MISS_TT
3553 cmp %g7, T_INSTR_MMU_MISS
3560 cmp %g7, T_INSTR_MMU_MISS
4010 CPU_INDEX(%g7, %g6)
4012 sllx %g7, KPMTSBM_SHIFT, %g7
4014 add %g6, %g7, %g6 /* g6 = kpmtsbm ptr */
4023 ldx [%g6 + KPMTSBM_VBASE], %g7
4024 cmp %g2, %g7
4056 sub %g2, %g7, %g4 /* paddr = vaddr-kpm_vbase */
4068 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmp2m)
4078 ldxa [%g3 + MEMSEG_KPM_PBASE]%asi, %g7
4081 sub %g4, %g7, %g4
4092 ld [%g6 + KPMTSBM_KPMPTABLESZ], %g7
4094 ld [%g6 + KPMTSBM_KPMPTABLESZ], %g7
4108 sub %g7, 1, %g7 /* mask */
4111 and %g5, %g7, %g5 /* hashinx = y & mask */
4151 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
4159 KPMLOCK_ENTER(%g3, %g7, kpmtsbmhdlr1, ASI_MEM)
4162 ldsha [%g1 + KPMPAGE_REFCNTC]%asi, %g7 /* kp_refcntc */
4163 cmp %g7, -1
4169 ldsha [%g1 + KPMPAGE_REFCNT]%asi, %g7
4170 brz,pn %g7, 5f /* let C-handler deal with this */
4175 ldub [%g6 + KPMTSBM_FLAGS], %g7
4177 andcc %g7, KPMTSBM_TSBPHYS_FLAG, %g0
4187 TSB_LOCK_ENTRY(%g4, %g1, %g7, locked_tsb_l1)
4190 TSB_INSERT_UNLOCK_ENTRY(%g4, %g5, %g2, %g7)
4203 rdpr %tl, %g7
4204 cmp %g7, 1
4207 rdpr %tpc, %g7
4209 cmp %g7, %g6
4212 add %g7, RUNTIME_PATCH, %g7 /* must match TSTAT_TSBMISS_INSTR */
4213 wrpr %g7, %tpc
4214 add %g7, 4, %g7
4215 wrpr %g7, %tnpc
4233 CPU_INDEX(%g7, %g6)
4235 sllx %g7, KPMTSBM_SHIFT, %g7
4237 add %g6, %g7, %g6 /* g6 = kpmtsbm ptr */
4249 ldx [%g6 + KPMTSBM_VBASE], %g7
4250 cmp %g2, %g7
4286 sub %g2, %g7, %g4 /* paddr = vaddr-kpm_vbase */
4287 srax %g4, %g3, %g7 /* which alias range (r) */
4288 brz,pt %g7, 2f
4294 sllx %g7, %g3, %g5 /* g5 = r << kpm_size_shift */
4295 cmp %g7, %g1 /* if (r > v) */
4298 sub %g7, %g1, %g5 /* g5 = r - v */
4299 sllx %g5, MMU_PAGESHIFT, %g7 /* (r-v) << MMU_PAGESHIFT */
4300 add %g4, %g7, %g4 /* paddr += (r-v)<<MMU_PAGESHIFT */
4304 sllx %g7, MMU_PAGESHIFT, %g5 /* else */
4328 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmsp2m)
4337 ldxa [%g3 + MEMSEG_KPM_PBASE]%asi, %g7
4338 sub %g2, %g7, %g4
4348 ld [%g6 + KPMTSBM_KPMPTABLESZ], %g7
4350 ld [%g6 + KPMTSBM_KPMPTABLESZ], %g7
4362 sub %g7, 1, %g7 /* mask */
4365 and %g5, %g7, %g5 /* hashinx = y & mask */
4397 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
4406 KPMLOCK_ENTER(%g3, %g7, kpmtsbsmlock, ASI_MEM)
4409 ldsba [%g1 + KPMSPAGE_MAPPED]%asi, %g7 /* kp_mapped */
4410 andcc %g7, KPM_MAPPED_GO, %g0 /* go or no go ? */
4413 and %g7, KPM_MAPPED_MASK, %g7 /* go */
4414 cmp %g7, KPM_MAPPEDS /* cacheable ? */
4419 ldub [%g6 + KPMTSBM_FLAGS], %g7
4421 andcc %g7, KPMTSBM_TSBPHYS_FLAG, %g0
4431 TSB_LOCK_ENTRY(%g4, %g1, %g7, locked_tsb_l2)
4434 TSB_INSERT_UNLOCK_ENTRY(%g4, %g5, %g2, %g7)
4447 rdpr %tl, %g7
4448 cmp %g7, 1
4451 rdpr %tpc, %g7
4453 cmp %g7, %g6
4456 add %g7, RUNTIME_PATCH, %g7 /* must match TSTAT_TSBMISS_INSTR */
4457 wrpr %g7, %tpc
4458 add %g7, 4, %g7
4459 wrpr %g7, %tnpc
4585 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
4591 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
4594 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
4600 GET_TSBE_POINTER(MMU_PAGESHIFT4M, %g3, %g7, %g6, %g5)