Home
last modified time | relevance | path

Searched refs:BIT (Results 1 – 25 of 62) sorted by relevance

123

/illumos-gate/usr/src/uts/common/io/yge/
H A Dyge.h97 #define BIT(n) (1U << n) macro
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
137 #define PCI_Y2_PHY2_POWD BIT(27) /* Set PHY 2 to Power Down (YUKON-2) */
138 #define PCI_Y2_PHY1_POWD BIT(26) /* Set PHY 1 to Power Down (YUKON-2) */
139 #define PCI_DIS_BOOT BIT(24) /* Disable BOOT via ROM */
140 #define PCI_EN_IO BIT(23) /* Mapping to I/O space */
141 #define PCI_EN_FPROM BIT(22) /* Enable FLASH mapping to memory */
[all …]
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-regs.h38 #define XGE_HAL_GEN_INTR_TXPIC BIT(0)
39 #define XGE_HAL_GEN_INTR_TXDMA BIT(1)
40 #define XGE_HAL_GEN_INTR_TXMAC BIT(2)
41 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3)
42 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8)
43 #define XGE_HAL_GEN_INTR_RXPIC BIT(32)
44 #define XGE_HAL_GEN_INTR_RXDMA BIT(33)
45 #define XGE_HAL_GEN_INTR_RXMAC BIT(34)
46 #define XGE_HAL_GEN_INTR_MC BIT(35)
47 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36)
[all …]
H A Dxgehal-fifo.h58 #define XGE_HAL_TX_FIFO_FIRST_LIST BIT(14)
59 #define XGE_HAL_TX_FIFO_LAST_LIST BIT(15)
61 #define XGE_HAL_TX_FIFO_SPECIAL_FUNC BIT(23)
94 #define XGE_HAL_TXD_LIST_OWN_XENA BIT(7)
95 #define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
98 #define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23))
99 #define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22)
100 #define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23)
110 #define XGE_HAL_TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
111 #define XGE_HAL_TXD_TX_CKO_IPV4_EN BIT(5)
[all …]
H A Dxgehal-ring.h58 #define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */
59 #define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */
60 #define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
72 #define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24)
73 #define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27)
74 #define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28)
75 #define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29)
76 #define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30)
77 #define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31)
212 (u8)((Control_1 & BIT(18))>>45)
[all …]
H A Dxgehal-types.h34 #define BIT(loc) (0x8000000000000000ULL >> (loc)) macro
547 #define XGE_HAL_TXPIC_INT_M BIT(0)
548 #define XGE_HAL_TXDMA_INT_M BIT(1)
549 #define XGE_HAL_TXMAC_INT_M BIT(2)
550 #define XGE_HAL_TXXGXS_INT_M BIT(3)
551 #define XGE_HAL_TXTRAFFIC_INT_M BIT(8)
552 #define XGE_HAL_PIC_RX_INT_M BIT(32)
553 #define XGE_HAL_RXDMA_INT_M BIT(33)
554 #define XGE_HAL_RXMAC_INT_M BIT(34)
555 #define XGE_HAL_MC_INT_M BIT(35)
[all …]
/illumos-gate/usr/src/uts/common/io/sdcard/adapters/sdhost/
H A Dsdhost.h48 #define BIT(x) (1 << (x)) macro
122 #define XFR_MODE_DMA_EN BIT(0)
123 #define XFR_MODE_COUNT BIT(1)
124 #define XFR_MODE_AUTO_CMD12 BIT(2)
125 #define XFR_MODE_READ BIT(4) /* 1 = read, 0 = write */
126 #define XFR_MODE_MULTI BIT(5) /* 1 = multi, 0 = single */
129 #define COMMAND_CRC_CHECK_EN BIT(3)
130 #define COMMAND_INDEX_CHECK_EN BIT(4)
131 #define COMMAND_DATA_PRESENT BIT(5)
144 #define PRS_CMD_INHIBIT BIT(0)
[all …]
/illumos-gate/usr/src/uts/intel/io/vmm/amd/
H A Dvmcb.h47 #define BIT(n) (1ULL << n) macro
62 #define VMCB_INTCPT_INTR BIT(0)
63 #define VMCB_INTCPT_NMI BIT(1)
64 #define VMCB_INTCPT_SMI BIT(2)
65 #define VMCB_INTCPT_INIT BIT(3)
66 #define VMCB_INTCPT_VINTR BIT(4)
67 #define VMCB_INTCPT_CR0_WRITE BIT(5)
68 #define VMCB_INTCPT_IDTR_READ BIT(6)
69 #define VMCB_INTCPT_GDTR_READ BIT(7)
70 #define VMCB_INTCPT_LDTR_READ BIT(8)
[all …]
H A Damdvi_priv.h37 #define BIT(n) (1ULL << (n)) macro
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
49 #define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
54 #define AMDVI_EX_FEA_PREFSUP BIT(0) /* Prefetch command support. */
55 #define AMDVI_EX_FEA_PPRSUP BIT(1) /* PPR support */
56 #define AMDVI_EX_FEA_XTSUP BIT(2) /* Reserved */
57 #define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
[all …]
/illumos-gate/usr/src/uts/common/io/rtw/
H A Drtwreg.h49 #define BIT(n) (((n) == 32) ? 0 : ((uint32_t)1 << (n))) macro
54 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
136 #define RTW_BRSR_BPLCP BIT(8)
146 #define RTW_BRSR_MBR8181_1MBPS BIT(0)
147 #define RTW_BRSR_MBR8181_2MBPS BIT(1)
148 #define RTW_BRSR_MBR8181_5MBPS BIT(2)
149 #define RTW_BRSR_MBR8181_11MBPS BIT(3)
170 #define RTW_CR_RST BIT(4)
177 #define RTW_CR_RE BIT(3)
184 #define RTW_CR_TE BIT(2)
[all …]
H A Dsa2400reg.h46 #define SA2400_TWI_WREN BIT(7) /* enable write */
58 #define SA2400_SYNA_FM BIT(21)
89 #define SA2400_SYNB_ON BIT(9)
90 #define SA2400_SYNB_ONE BIT(8) /* always 1 */
111 #define SA2400_SYNC_ZERO BIT(2) /* always 0 */
120 #define SA2400_SYND_TPHPSU BIT(16)
125 #define SA2400_SYND_TPSU BIT(15)
136 #define SA2400_OPMODE_ADC BIT(19)
141 #define SA2400_OPMODE_FTERR BIT(18)
151 #define SA2400_OPMODE_V2P5 BIT(14)
[all …]
H A Dmax2820reg.h58 #define MAX2820_ENABLE_RSVD1 BIT(11) /* reserved */
63 #define MAX2820_ENABLE_PAB BIT(10)
68 #define MAX2820_ENABLE_TXFLT BIT(9)
73 #define MAX2820_ENABLE_TXUVD BIT(8)
78 #define MAX2820_ENABLE_DET BIT(7)
83 #define MAX2820_ENABLE_RXDFA BIT(6)
88 #define MAX2820_ENABLE_RXLNA BIT(5)
93 #define MAX2820_ENABLE_AT BIT(4)
98 #define MAX2820_ENABLE_CP BIT(3)
103 #define MAX2820_ENABLE_PLL BIT(2)
[all …]
H A Dsi4136reg.h72 #define SI4126_MAIN_XINDIV2 BIT(6) /* 1: divide crystal input (XIN) by 2 */
73 #define SI4126_MAIN_LPWR BIT(5) /* 1: low-power mode */
79 #define SI4126_MAIN_AUTOPDB BIT(3)
86 #define SI4126_POWER_PDIB BIT(1) /* 1: IF synthesizer on */
87 #define SI4126_POWER_PDRB BIT(0) /* 1: RF synthesizer on */
/illumos-gate/usr/src/uts/common/io/audio/drv/audiocmi/
H A Daudiocmi.h73 #define FUNCTRL0_CH1_RST BIT(19)
74 #define FUNCTRL0_CH0_RST BIT(18)
75 #define FUNCTRL0_CH1_EN BIT(17)
76 #define FUNCTRL0_CH0_EN BIT(16)
77 #define FUNCTRL0_CH1_PAUSE BIT(3)
78 #define FUNCTRL0_CH0_PAUSE BIT(2)
79 #define FUNCTRL0_CH1_REC BIT(1)
80 #define FUNCTRL0_CH0_REC BIT(0)
100 #define FUNCTRL1_INTRM BIT(5) /* enable MCB intr */
101 #define FUNCTRL1_BREQ BIT(4) /* bus master enable */
[all …]
/illumos-gate/usr/src/cmd/cmd-inet/usr.lib/wpad/
H A Dwpa_impl.h22 #define BIT(n) (1 << (n)) macro
24 #define WPA_CIPHER_NONE BIT(0)
25 #define WPA_CIPHER_WEP40 BIT(1)
26 #define WPA_CIPHER_WEP104 BIT(2)
27 #define WPA_CIPHER_TKIP BIT(3)
28 #define WPA_CIPHER_CCMP BIT(4)
30 #define WPA_KEY_MGMT_IEEE8021X BIT(0)
31 #define WPA_KEY_MGMT_PSK BIT(1)
32 #define WPA_KEY_MGMT_NONE BIT(2)
33 #define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
[all …]
/illumos-gate/usr/src/uts/common/io/ena/
H A Dena_hw.h100 #define BIT(b) (1UL << (b)) macro
339 #define ENAHW_AENQ_DESC_PHASE_MASK BIT(0)
344 #define ENAHW_AENQ_LINK_CHANGE_LINK_STATUS_MASK BIT(0)
521 #define ENAHW_HOST_INFO_RX_OFFSET_MASK BIT(1)
523 #define ENAHW_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
525 #define ENAHW_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
527 #define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
529 #define ENAHW_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)
531 #define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7)
533 #define ENAHW_HOST_INFO_INFO_PHC_MASK BIT(8)
[all …]
H A Dena_aenq.c84 to_enable = BIT(ENAHW_AENQ_GROUP_LINK_CHANGE) | in ena_aenq_configure()
85 BIT(ENAHW_AENQ_GROUP_FATAL_ERROR) | in ena_aenq_configure()
86 BIT(ENAHW_AENQ_GROUP_WARNING) | in ena_aenq_configure()
87 BIT(ENAHW_AENQ_GROUP_NOTIFICATION) | in ena_aenq_configure()
88 BIT(ENAHW_AENQ_GROUP_KEEP_ALIVE) | in ena_aenq_configure()
89 BIT(ENAHW_AENQ_GROUP_DEVICE_REQUEST_RESET); in ena_aenq_configure()
112 bool supported = BIT(grpstr->eag_type) & in ena_aenq_configure()
114 bool enabled = BIT(grpstr->eag_type) & in ena_aenq_configure()
/illumos-gate/usr/src/contrib/ast/src/lib/libcmd/
H A Dstty.c100 #define BIT 1 macro
203 { "parenb", BIT, C_FLAG, 0, PARENB, PARENB, C("Enable (disable) parity generation and detection") },
204 { "parodd", BIT, C_FLAG, 0, PARODD, PARODD, C("Use odd (even) parity") },
206 { "parext", BIT, C_FLAG, 0, PAREXT, PAREXT },
209 { "cread", BIT, C_FLAG, SS, CREAD, CREAD, C("Enable (disable) input") },
215 { "hupcl", BIT, C_FLAG, 0, HUPCL, HUPCL, C("Hangup (do not hangup) connection on last close") },
216 { "hup", BIT, C_FLAG, IG, HUPCL, HUPCL, C("Same as \bhupcl\b") },
217 { "cstopb", BIT, C_FLAG, 0, CSTOPB, CSTOPB, C("Use two (one) stop bits") },
219 { "crtscts", BIT, C_FLAG, 0, CRTSCTS, CRTSCTS, C("Enable (disable) RTS/CTS handshaking") },
221 { "clocal", BIT, C_FLAG, NL, CLOCAL, CLOCAL, C("Disable (enable) modem control signals") },
[all …]
/illumos-gate/usr/src/uts/common/io/arn/
H A Darn_core.h328 BUF_DATA = BIT(0),
329 BUF_AGGR = BIT(1),
330 BUF_AMPDU = BIT(2),
331 BUF_HT = BIT(3),
332 BUF_RETRY = BIT(4),
333 BUF_XRETRY = BIT(5),
334 BUF_SHORT_PREAMBLE = BIT(6),
335 BUF_BAR = BIT(7),
336 BUF_PSPOLL = BIT(8),
337 BUF_AGGR_BURST = BIT(9),
[all …]
H A Darn_rc.h238 ATH9K_TX_RC_USE_RTS_CTS = BIT(0),
239 ATH9K_TX_RC_USE_CTS_PROTECT = BIT(1),
240 ATH9K_TX_RC_USE_SHORT_PREAMBLE = BIT(2),
241 ATH9K_TX_RC_MCS = BIT(3),
242 ATH9K_TX_RC_GREEN_FIELD = BIT(4),
243 ATH9K_TX_RC_40_MHZ_WIDTH = BIT(5),
244 ATH9K_TX_RC_DUP_DATA = BIT(6),
245 ATH9K_TX_RC_SHORT_GI = BIT(7),
H A Darn_ath9k.h66 #define BIT(n) (1UL << (n)) macro
199 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
200 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
201 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
202 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
203 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
204 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
205 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
206 ATH9K_HW_CAP_VEOL = BIT(7),
207 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
[all …]
/illumos-gate/usr/src/uts/common/io/i40e/core/
H A Dvirtchnl.h91 VIRTCHNL_LINK_SPEED_100MB = BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT),
92 VIRTCHNL_LINK_SPEED_1GB = BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT),
93 VIRTCHNL_LINK_SPEED_10GB = BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT),
94 VIRTCHNL_LINK_SPEED_40GB = BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT),
95 VIRTCHNL_LINK_SPEED_20GB = BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT),
96 VIRTCHNL_LINK_SPEED_25GB = BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT),
97 VIRTCHNL_LINK_SPEED_2_5GB = BIT(VIRTCHNL_LINK_SPEED_2_5GB_SHIFT),
98 VIRTCHNL_LINK_SPEED_5GB = BIT(VIRTCHNL_LINK_SPEED_5GB_SHIFT),
H A Di40e_dcb.h92 #define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)
94 #define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)
115 #define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)
117 #define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)
/illumos-gate/usr/src/boot/libsa/string/
H A Dstrcspn.c35 #define BIT(c) ((u_long)1 << ((u_char)(c) % LONG_BIT)) macro
61 bit = BIT(*charset); in strcspn()
67 bit = BIT(*s1); in strcspn()
H A Dstrspn.c35 #define BIT(c) ((u_long)1 << ((u_char)(c) % LONG_BIT)) macro
60 bit = BIT(*charset); in strspn()
66 bit = BIT(*s1); in strspn()
/illumos-gate/usr/src/cmd/lastcomm/
H A Dlc_utils.c266 #define BIT(flag, ch) flags[i++] = (f & flag) ? ch : ' ' in flagbits() macro
267 BIT(ASU, 'S'); in flagbits()
268 BIT(AFORK, 'F'); in flagbits()
271 #undef BIT in flagbits()

123