Lines Matching refs:BIT
100 #define BIT(b) (1UL << (b)) macro
339 #define ENAHW_AENQ_DESC_PHASE_MASK BIT(0)
344 #define ENAHW_AENQ_LINK_CHANGE_LINK_STATUS_MASK BIT(0)
521 #define ENAHW_HOST_INFO_RX_OFFSET_MASK BIT(1)
523 #define ENAHW_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
525 #define ENAHW_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
527 #define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
529 #define ENAHW_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)
531 #define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7)
533 #define ENAHW_HOST_INFO_INFO_PHC_MASK BIT(8)
602 #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_MASK (BIT(5))
722 #define ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG_MASK BIT(0)
835 #define ENAHW_CMD_PHASE_MASK BIT(0)
1097 #define ENAHW_FEAT_LINK_CONF_AUTONEG_MASK BIT(0)
1099 #define ENAHW_FEAT_LINK_CONF_DUPLEX_MASK BIT(1)
1149 #define ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM_MASK BIT(0)
1151 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1153 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1155 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1157 #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1159 #define ENAHW_FEAT_OFFLOAD_TSO_IPV4_MASK BIT(5)
1161 #define ENAHW_FEAT_OFFLOAD_TSO_IPV6_MASK BIT(6)
1163 #define ENAHW_FEAT_OFFLOAD_TSO_ECN_MASK BIT(7)
1164 #define ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM_MASK BIT(0)
1166 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_MASK BIT(1)
1168 #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_MASK BIT(2)
1170 #define ENAHW_FEAT_OFFLOAD_RX_HASH_MASK BIT(3)
1569 #define ENAHW_TX_DESC_META_DESC_MASK BIT(23)
1571 #define ENAHW_TX_DESC_PHASE_MASK BIT(24)
1573 #define ENAHW_TX_DESC_FIRST_MASK BIT(26)
1575 #define ENAHW_TX_DESC_LAST_MASK BIT(27)
1577 #define ENAHW_TX_DESC_COMP_REQ_MASK BIT(28)
1580 #define ENAHW_TX_DESC_DF_MASK BIT(4)
1582 #define ENAHW_TX_DESC_TSO_EN_MASK BIT(7)
1586 #define ENAHW_TX_DESC_L3_CSUM_EN_MASK BIT(13)
1588 #define ENAHW_TX_DESC_L4_CSUM_EN_MASK BIT(14)
1590 #define ENAHW_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
1592 #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
1759 #define ENAHW_TX_CDESC_PHASE_MASK BIT(0)
1806 #define ENAHW_RX_DESC_PHASE_MASK BIT(0)
1808 #define ENAHW_RX_DESC_FIRST_MASK BIT(2)
1810 #define ENAHW_RX_DESC_LAST_MASK BIT(3)
1812 #define ENAHW_RX_DESC_COMP_REQ_MASK BIT(4)
1910 #define ENAHW_RX_CDESC_L3_CSUM_ERR_MASK BIT(13)
1912 #define ENAHW_RX_CDESC_L4_CSUM_ERR_MASK BIT(14)
1914 #define ENAHW_RX_CDESC_IPV4_FRAG_MASK BIT(15)
1916 #define ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK BIT(16)
1918 #define ENAHW_RX_CDESC_PHASE_MASK BIT(24)
1920 #define ENAHW_RX_CDESC_L3_CSUM2_MASK BIT(25)
1922 #define ENAHW_RX_CDESC_FIRST_MASK BIT(26)
1924 #define ENAHW_RX_CDESC_LAST_MASK BIT(27)
1926 #define ENAHW_RX_CDESC_BUFFER_MASK BIT(30)
1966 #define ENAHW_REG_INTR_UNMASK_MASK BIT(30)