1a72f7ea6Sql147931 /* 2*9aa73b68SQin Michael Li * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3a72f7ea6Sql147931 * Use is subject to license terms. 4a72f7ea6Sql147931 */ 5a72f7ea6Sql147931 6a72f7ea6Sql147931 /* 7a72f7ea6Sql147931 * Copyright (c) 2004 David Young. All rights reserved. 8a72f7ea6Sql147931 * 9a72f7ea6Sql147931 * This code was written by David Young. 10a72f7ea6Sql147931 * 11a72f7ea6Sql147931 * Redistribution and use in source and binary forms, with or without 12a72f7ea6Sql147931 * modification, are permitted provided that the following conditions 13a72f7ea6Sql147931 * are met: 14a72f7ea6Sql147931 * 1. Redistributions of source code must retain the above copyright 15a72f7ea6Sql147931 * notice, this list of conditions and the following disclaimer. 16a72f7ea6Sql147931 * 2. Redistributions in binary form must reproduce the above copyright 17a72f7ea6Sql147931 * notice, this list of conditions and the following disclaimer in the 18a72f7ea6Sql147931 * documentation and/or other materials provided with the distribution. 19a72f7ea6Sql147931 * 3. Neither the name of the author nor the names of any co-contributors 20a72f7ea6Sql147931 * may be used to endorse or promote products derived from this software 21a72f7ea6Sql147931 * without specific prior written permission. 22a72f7ea6Sql147931 * 23a72f7ea6Sql147931 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 24a72f7ea6Sql147931 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25a72f7ea6Sql147931 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 26a72f7ea6Sql147931 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 27a72f7ea6Sql147931 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28a72f7ea6Sql147931 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 29a72f7ea6Sql147931 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30a72f7ea6Sql147931 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 31a72f7ea6Sql147931 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32a72f7ea6Sql147931 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33a72f7ea6Sql147931 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34a72f7ea6Sql147931 * OF SUCH DAMAGE. 35a72f7ea6Sql147931 */ 36a72f7ea6Sql147931 #ifndef _MAX2820REG_H_ 37a72f7ea6Sql147931 #define _MAX2820REG_H_ 38a72f7ea6Sql147931 39*9aa73b68SQin Michael Li #ifdef __cplusplus 40*9aa73b68SQin Michael Li extern "C" { 41*9aa73b68SQin Michael Li #endif 42*9aa73b68SQin Michael Li 43a72f7ea6Sql147931 /* 44a72f7ea6Sql147931 * Serial bus format for Maxim MAX2820/MAX2820A/MAX2821/MAX2821A 45a72f7ea6Sql147931 * 2.4GHz 802.11b Zero-IF Transceivers 46a72f7ea6Sql147931 */ 47a72f7ea6Sql147931 #define MAX2820_TWI_ADDR_MASK BITS(15, 12) 48a72f7ea6Sql147931 #define MAX2820_TWI_DATA_MASK BITS(11, 0) 49a72f7ea6Sql147931 50a72f7ea6Sql147931 /* 51a72f7ea6Sql147931 * Registers for Maxim MAX2820/MAX2820A/MAX2821/MAX2821A 2.4GHz 52a72f7ea6Sql147931 * 802.11b Zero-IF Transceivers 53a72f7ea6Sql147931 */ 54a72f7ea6Sql147931 #define MAX2820_TEST 0 /* Test Register */ 55a72f7ea6Sql147931 #define MAX2820_TEST_DEFAULT BITS(2, 0) /* Always set to this value. */ 56a72f7ea6Sql147931 57a72f7ea6Sql147931 #define MAX2820_ENABLE 1 /* Block-Enable Register */ 58a72f7ea6Sql147931 #define MAX2820_ENABLE_RSVD1 BIT(11) /* reserved */ 59a72f7ea6Sql147931 /* 60a72f7ea6Sql147931 * Transmit Baseband Filters Enable 61a72f7ea6Sql147931 * PAB_EN = SHDNB && (MAX2820_ENABLE_PAB || TX_ON) 62a72f7ea6Sql147931 */ 63a72f7ea6Sql147931 #define MAX2820_ENABLE_PAB BIT(10) 64a72f7ea6Sql147931 /* 65a72f7ea6Sql147931 * Transmit Baseband Filters Enable 66a72f7ea6Sql147931 * TXFLT_EN = SHDNB && (MAX2820_ENABLE_TXFLT || TX_ON) 67a72f7ea6Sql147931 */ 68a72f7ea6Sql147931 #define MAX2820_ENABLE_TXFLT BIT(9) 69a72f7ea6Sql147931 /* 70a72f7ea6Sql147931 * Tx Upconverter, VGA, and Driver Amp Enable 71a72f7ea6Sql147931 * TXUVD_EN = SHDNB && (MAX2820_ENABLE_TXUVD || TX_ON) 72a72f7ea6Sql147931 */ 73a72f7ea6Sql147931 #define MAX2820_ENABLE_TXUVD BIT(8) 74a72f7ea6Sql147931 /* 75a72f7ea6Sql147931 * Receive Detector Enable 76a72f7ea6Sql147931 * DET_EN = SHDNB && (MAX2820_ENABLE_DET || RX_ON) 77a72f7ea6Sql147931 */ 78a72f7ea6Sql147931 #define MAX2820_ENABLE_DET BIT(7) 79a72f7ea6Sql147931 /* 80a72f7ea6Sql147931 * Rx Downconverter, Filters, and AGC Amps Enable 81a72f7ea6Sql147931 * RXDFA_EN = SHDNB && (MAX2820_ENABLE_RXDFA || RX_ON) 82a72f7ea6Sql147931 */ 83a72f7ea6Sql147931 #define MAX2820_ENABLE_RXDFA BIT(6) 84a72f7ea6Sql147931 /* 85a72f7ea6Sql147931 * Receive LNA Enable 86a72f7ea6Sql147931 * AT_EN = SHDNB && (MAX2820_ENABLE_RXLNA || RX_ON) 87a72f7ea6Sql147931 */ 88a72f7ea6Sql147931 #define MAX2820_ENABLE_RXLNA BIT(5) 89a72f7ea6Sql147931 /* 90a72f7ea6Sql147931 * Auto-tuner Enable 91a72f7ea6Sql147931 * AT_EN = SHDNB && (MAX2820_ENABLE_AT || RX_ON || TX_ON) 92a72f7ea6Sql147931 */ 93a72f7ea6Sql147931 #define MAX2820_ENABLE_AT BIT(4) 94a72f7ea6Sql147931 /* 95a72f7ea6Sql147931 * PLL Charge-Pump Enable 96a72f7ea6Sql147931 * CP_EN = SHDNB && MAX2820_ENABLE_CP 97a72f7ea6Sql147931 */ 98a72f7ea6Sql147931 #define MAX2820_ENABLE_CP BIT(3) 99a72f7ea6Sql147931 /* 100a72f7ea6Sql147931 * PLL Enable 101a72f7ea6Sql147931 * PLL_EN = SHDNB && MAX2820_ENABLE_PLL 102a72f7ea6Sql147931 */ 103a72f7ea6Sql147931 #define MAX2820_ENABLE_PLL BIT(2) 104a72f7ea6Sql147931 /* 105a72f7ea6Sql147931 * VCO Enable 106a72f7ea6Sql147931 * VCO_EN = SHDNB && MAX2820_ENABLE_VCO 107a72f7ea6Sql147931 */ 108a72f7ea6Sql147931 #define MAX2820_ENABLE_VCO BIT(1) 109a72f7ea6Sql147931 #define MAX2820_ENABLE_RSVD0 BIT(0) /* reserved */ 110a72f7ea6Sql147931 #define MAX2820_ENABLE_DEFAULT \ 111a72f7ea6Sql147931 (MAX2820_ENABLE_AT|MAX2820_ENABLE_CP|\ 112a72f7ea6Sql147931 MAX2820_ENABLE_PLL|MAX2820_ENABLE_VCO) 113a72f7ea6Sql147931 114a72f7ea6Sql147931 #define MAX2820_SYNTH 2 /* Synthesizer Register */ 115a72f7ea6Sql147931 #define MAX2820_SYNTH_RSVD0 BITS(11, 7) /* reserved */ 116a72f7ea6Sql147931 /* 117a72f7ea6Sql147931 * Charge-Pump Current Select 118a72f7ea6Sql147931 * 0 = +/-1mA 119a72f7ea6Sql147931 * 1 = +/-2mA 120a72f7ea6Sql147931 */ 121a72f7ea6Sql147931 #define MAX2820_SYNTH_ICP BIT(6) 122a72f7ea6Sql147931 /* 123a72f7ea6Sql147931 * Reference Frequency Divider 124a72f7ea6Sql147931 * 0 = 22MHz 125a72f7ea6Sql147931 * 1 = 44MHz 126a72f7ea6Sql147931 */ 127a72f7ea6Sql147931 #define MAX2820_SYNTH_R_MASK BITS(5, 0) 128a72f7ea6Sql147931 #define MAX2820_SYNTH_R_22MHZ LSHIFT(0, MAX2820_SYNTH_R_MASK) 129a72f7ea6Sql147931 #define MAX2820_SYNTH_R_44MHZ LSHIFT(1, MAX2820_SYNTH_R_MASK) 130a72f7ea6Sql147931 #define MAX2820_SYNTH_ICP_DEFAULT MAX2820_SYNTH_ICP 131a72f7ea6Sql147931 #define MAX2820_SYNTH_R_DEFAULT LSHIFT(0, MAX2820_SYNTH_R_MASK) 132a72f7ea6Sql147931 133a72f7ea6Sql147931 #define MAX2820_CHANNEL 3 /* Channel Frequency Register */ 134a72f7ea6Sql147931 #define MAX2820_CHANNEL_RSVD BITS(11, 7) /* reserved */ 135a72f7ea6Sql147931 /* 136a72f7ea6Sql147931 * Channel Frequency Select 137a72f7ea6Sql147931 * fLO = 2400MHz + CF * 1MHz 138a72f7ea6Sql147931 */ 139a72f7ea6Sql147931 #define MAX2820_CHANNEL_CF_MASK BITS(6, 0) 140a72f7ea6Sql147931 #define MAX2820_CHANNEL_RSVD_DEFAULT LSHIFT(0, MAX2820_CHANNEL_RSVD) 141a72f7ea6Sql147931 #define MAX2820_CHANNEL_CF_DEFAULT LSHIFT(37, MAX2820_CHANNEL_CF_MASK) 142a72f7ea6Sql147931 143a72f7ea6Sql147931 /* 144a72f7ea6Sql147931 * Receiver Settings Register 145a72f7ea6Sql147931 * MAX2820/MAX2821 146a72f7ea6Sql147931 */ 147a72f7ea6Sql147931 #define MAX2820_RECEIVE 4 148a72f7ea6Sql147931 /* 149a72f7ea6Sql147931 * VGA DC Offset Nulling Parameter 2 150a72f7ea6Sql147931 */ 151a72f7ea6Sql147931 #define MAX2820_RECEIVE_2C_MASK BITS(11, 9) 152a72f7ea6Sql147931 /* 153a72f7ea6Sql147931 * VGA DC Offset Nulling Parameter 1 154a72f7ea6Sql147931 */ 155a72f7ea6Sql147931 #define MAX2820_RECEIVE_1C_MASK BITS(8, 6) 156a72f7ea6Sql147931 /* 157a72f7ea6Sql147931 * Rx Level Detector Midpoint 158a72f7ea6Sql147931 * Select 159a72f7ea6Sql147931 * 11, 01 = 50.2mVp 160a72f7ea6Sql147931 * 10 = 70.9mVp 161a72f7ea6Sql147931 * 00 = 35.5mVp 162a72f7ea6Sql147931 */ 163a72f7ea6Sql147931 #define MAX2820_RECEIVE_DL_MASK BITS(5, 4) 164a72f7ea6Sql147931 /* 165a72f7ea6Sql147931 * Special Function Select 166a72f7ea6Sql147931 * 0 = OFF 167a72f7ea6Sql147931 * 1 = ON 168a72f7ea6Sql147931 */ 169a72f7ea6Sql147931 #define MAX2820_RECEIVE_SF BIT(3) 170a72f7ea6Sql147931 /* 171a72f7ea6Sql147931 * Receive Filter -3dB Frequency 172a72f7ea6Sql147931 * Select (all frequencies are 173a72f7ea6Sql147931 * approximate) 174a72f7ea6Sql147931 */ 175a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_MASK BITS(2, 0) 176a72f7ea6Sql147931 /* 8.5MHz */ 177a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_8_5MHZ LSHIFT(0, MAX2820_RECEIVE_BW_MASK) 178a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_8MHZ LSHIFT(1, MAX2820_RECEIVE_BW_MASK) 179a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_7_5MHZ LSHIFT(2, MAX2820_RECEIVE_BW_MASK) 180a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_7MHZ LSHIFT(3, MAX2820_RECEIVE_BW_MASK) 181a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_6_5MHZ LSHIFT(4, MAX2820_RECEIVE_BW_MASK) 182a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_6MHZ LSHIFT(5, MAX2820_RECEIVE_BW_MASK) 183a72f7ea6Sql147931 #define MAX2820_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_2C_MASK) 184a72f7ea6Sql147931 #define MAX2820_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_1C_MASK) 185a72f7ea6Sql147931 #define MAX2820_RECEIVE_DL_DEFAULT LSHIFT(1, MAX2820_RECEIVE_DL_MASK) 186a72f7ea6Sql147931 #define MAX2820_RECEIVE_SF_DEFAULT LSHIFT(0, MAX2820_RECEIVE_SF) 187a72f7ea6Sql147931 #define MAX2820_RECEIVE_BW_DEFAULT MAX2820_RECEIVE_BW_7_5MHZ 188a72f7ea6Sql147931 189a72f7ea6Sql147931 /* 190a72f7ea6Sql147931 * Receiver Settings Register, 191a72f7ea6Sql147931 * MAX2820A/MAX2821A 192a72f7ea6Sql147931 */ 193a72f7ea6Sql147931 #define MAX2820A_RECEIVE 4 194a72f7ea6Sql147931 /* VGA DC Offset Nulling Parameter 2 */ 195a72f7ea6Sql147931 #define MAX2820A_RECEIVE_2C_MASK BITS(11, 9) 196a72f7ea6Sql147931 #define MAX2820A_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_2C_MASK) 197a72f7ea6Sql147931 /* VGA DC Offset Nulling Parameter 1 */ 198a72f7ea6Sql147931 #define MAX2820A_RECEIVE_1C_MASK BITS(8, 6) 199a72f7ea6Sql147931 #define MAX2820A_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_1C_MASK) 200a72f7ea6Sql147931 #define MAX2820A_RECEIVE_RSVD0_MASK BITS(5, 3) 201a72f7ea6Sql147931 #define MAX2820A_RECEIVE_RSVD0_DEFAULT LSHIFT(2, MAX2820A_RECEIVE_RSVD0_MASK) 202a72f7ea6Sql147931 #define MAX2820A_RECEIVE_RSVD1_MASK BITS(2, 0) 203a72f7ea6Sql147931 #define MAX2820A_RECEIVE_RSVD1_DEFAULT LSHIFT(2, MAX2820_RECEIVE_RSVD1_MASK) 204a72f7ea6Sql147931 205a72f7ea6Sql147931 #define MAX2820_TRANSMIT 5 /* Transmitter Settings Reg. */ 206a72f7ea6Sql147931 #define MAX2820_TRANSMIT_RSVD_MASK BITS(11, 4) /* reserved */ 207a72f7ea6Sql147931 /* 208a72f7ea6Sql147931 * PA Bias Select 209a72f7ea6Sql147931 * 15 = Highest 210a72f7ea6Sql147931 * 0 = Lowest 211a72f7ea6Sql147931 */ 212a72f7ea6Sql147931 #define MAX2820_TRANSMIT_PA_MASK BITS(3, 0) 213a72f7ea6Sql147931 #define MAX2820_TRANSMIT_PA_DEFAULT LSHIFT(0, MAX2820_TRANSMIT_PA_MASK) 214a72f7ea6Sql147931 215*9aa73b68SQin Michael Li #ifdef __cplusplus 216*9aa73b68SQin Michael Li } 217*9aa73b68SQin Michael Li #endif 218*9aa73b68SQin Michael Li 219a72f7ea6Sql147931 #endif /* _MAX2820REG_H_ */ 220