| /freebsd/sys/dev/mmc/ |
| H A D | mmc.c | 190 static bool mmc_host_timing(device_t dev, enum mmc_bus_timing timing);
212 enum mmc_bus_timing timing);
216 enum mmc_bus_timing timing);
218 enum mmc_bus_timing timing);
225 enum mmc_bus_timing timing);
226 static const char *mmc_timing_to_string(enum mmc_bus_timing timing);
321 enum mmc_bus_timing timing; in mmc_acquire_bus() local
349 timing = mmcbr_get_timing(busdev); in mmc_acquire_bus()
362 if (timing >= bus_timing_mmc_ddr52 && in mmc_acquire_bus()
371 mmc_timing_to_string(timing)); in mmc_acquire_bus()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | sdhci-sprd.txt | 33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
|
| H A D | exynos-dw-mshc.txt | 32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
37 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
41 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
44 Notes for the sdr-timing and ddr-timing values:
50 Valid values for SDR and DDR CIU clock timing for Exynos5250:
89 samsung,dw-mshc-sdr-timing = <2 3>;
90 samsung,dw-mshc-ddr-timing = <1 2>;
91 samsung,dw-mshc-hs400-timing = <0 2>;
|
| /freebsd/sys/contrib/device-tree/Bindings/mips/cavium/ |
| H A D | bootbus.txt | 32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | nvidia,tegra124-car.txt | 29 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set
32 Each "emc-timings" node should contain a "timing" subnode for every supported
35 Required properties for "timing" nodes :
36 - clock-frequency : Should contain the memory clock rate to which this timing
39 parent of the EMC clock should be running at this timing.
44 timing.
93 timing-12750000 {
99 timing-20400000 {
|
| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | ahci-ceva.txt | 8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
25 - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
33 - ceva,p1-retry-params: Retry interval timing value for port 1.
|
| /freebsd/sys/dev/drm2/ |
| H A D | drm_edid.c | 578 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
901 struct detailed_timing *timing, in drm_mode_detailed() argument
905 struct detailed_pixel_timing *pt = &timing->data.pixel_data; in drm_mode_detailed()
947 timing->pixel_clock = cpu_to_le16(1088); in drm_mode_detailed()
949 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; in drm_mode_detailed()
1050 struct detailed_timing *timing) in mode_in_range() argument
1053 u8 *t = (u8 *)timing; in mode_in_range()
1096 struct detailed_timing *timing) in drm_dmt_modes_for_range() argument
1103 if (mode_in_range(drm_dmt_modes + i, edid, timing) && in drm_dmt_modes_for_range()
1131 struct detailed_timing *timing) in drm_gtf_modes_for_range() argument
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/media/xilinx/ |
| H A D | xlnx,v-tc.txt | 4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
|
| H A D | xlnx,v-tpg.txt | 29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
|
| /freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
| H A D | tegra124-nyan-blaze-emc.dtsi | 10 timing-12750000 {
17 timing-20400000 {
24 timing-40800000 {
31 timing-68000000 {
38 timing-102000000 {
45 timing-204000000 {
52 timing-300000000 {
59 timing-396000000 {
68 timing-600000000 {
75 timing-792000000 {
[all …]
|
| H A D | tegra124-apalis-emc.dtsi | 14 timing-12750000 {
21 timing-20400000 {
28 timing-40800000 {
35 timing-68000000 {
42 timing-102000000 {
49 timing-204000000 {
56 timing-300000000 {
63 timing-396000000 {
70 timing-528000000 {
77 timing-600000000 {
[all …]
|
| H A D | tegra30-asus-tf300tg.dts | 224 timing-25500000 {
234 timing-51000000 {
244 timing-102000000 {
254 timing-204000000 {
264 timing-333500000 {
274 timing-667000000 {
289 timing-25500000 {
299 timing-51000000 {
309 timing-102000000 {
319 timing-204000000 {
[all …]
|
| H A D | tegra124-jetson-tk1-emc.dtsi | 10 timing-12750000 {
17 timing-20400000 {
24 timing-40800000 {
31 timing-68000000 {
38 timing-102000000 {
45 timing-204000000 {
52 timing-300000000 {
59 timing-396000000 {
66 timing-528000000 {
73 timing-600000000 {
[all …]
|
| H A D | tegra30-asus-tf300t.dts | 150 timing-25500000 {
160 timing-51000000 {
170 timing-102000000 {
180 timing-204000000 {
190 timing-333500000 {
200 timing-667000000 {
215 timing-25500000 {
225 timing-51000000 {
235 timing-102000000 {
245 timing-204000000 {
[all …]
|
| H A D | tegra30-asus-tf201.dts | 116 timing-25500000 {
126 timing-51000000 {
136 timing-102000000 {
146 timing-204000000 {
156 timing-400000000 {
171 timing-25500000 {
181 timing-51000000 {
191 timing-102000000 {
201 timing-204000000 {
211 timing-500000000 {
[all …]
|
| H A D | tegra30-asus-tf700t.dts | 145 timing-25500000 {
155 timing-51000000 {
165 timing-102000000 {
175 timing-204000000 {
185 timing-400000000 {
195 timing-800000000 {
210 timing-25500000 {
220 timing-51000000 {
230 timing-102000000 {
240 timing
[all...] |
| H A D | tegra30-lg-p895.dts | 120 timing-12750000 {
130 timing-25500000 {
140 timing-51000000 {
150 timing-102000000 {
160 timing-204000000 {
170 timing-266500000 {
180 timing-533000000 {
197 timing-12750000 {
232 timing-25500000 {
267 timing-51000000 {
[all …]
|
| H A D | tegra30-lg-p880.dts | 124 timing-12750000 {
134 timing-25500000 {
144 timing-51000000 {
154 timing-102000000 {
164 timing-204000000 {
174 timing-266500000 {
184 timing-533000000 {
201 timing-12750000 {
237 timing-25500000 {
273 timing-51000000 {
[all …]
|
| H A D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 8 timing-25500000 {
33 timing-51000000 {
58 timing-102000000 {
83 timing-204000000 {
108 timing-333500000 {
133 timing-667000000 {
162 timing-25500000 {
187 timing-51000000 {
212 timing-102000000 {
237 timing-204000000 {
[all …]
|
| /freebsd/sys/dev/ow/ |
| H A D | owll_if.m | 44 # Maxim datasheets also describe how to use UARTs to generate timing,
47 # Chapter 4 has all the electrical timing diagrams that make up the link
94 struct ow_timing *timing; /* timing values */
112 struct ow_timing *timing; /* timing values */
130 struct ow_timing *timing; /* timing values */
154 struct ow_timing *timing; /* timing values */
|
| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6qdl-tx6-lvds.dtsi | 130 timing-hsd100pxn1 {
144 timing-vga {
160 timing-nl12880bc20 {
176 timing-et0700 {
192 timing-etv570 {
223 timing-hsd100pxn1 {
237 timing-vga {
253 timing-nl12880bc20 {
|
| H A D | imx6qdl-tx6-lcd.dtsi | 113 timing-vga {
129 timing-etv570 {
145 timing-et0350 {
161 timing-et0430 {
177 timing-et0500 {
193 timing-et0700 { /* same as ET0500 */
209 timing-etq570 {
225 timing-comtft { /* same as ET0700 but with inverted pixel clock */
|
| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos5410-smdk5410.dts | 71 samsung,dw-mshc-sdr-timing = <2 3>;
72 samsung,dw-mshc-ddr-timing = <1 2>;
81 samsung,dw-mshc-sdr-timing = <2 3>;
82 samsung,dw-mshc-ddr-timing = <1 2>;
128 samsung,srom-timing = <9 12 1 9 1 1>;
|
| H A D | exynos5260-xyref5260.dts | 99 samsung,dw-mshc-sdr-timing = <0 4>;
100 samsung,dw-mshc-ddr-timing = <0 2>;
111 samsung,dw-mshc-sdr-timing = <2 3>;
112 samsung,dw-mshc-ddr-timing = <1 2>;
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | imx-weim.txt | 58 - fsl,weim-cs-timing: The timing array, contains timing values for the
88 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
95 In this case, both chip select 0 and 1 will be configured with the same timing
114 fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
|