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Searched refs:simm5 (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dsifive_vector.h49 #define __riscv_sf_vc_i_se_u8mf4(p27_26, p24_20, p11_7, simm5, vl) \ argument
50 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 7, vl)
51 #define __riscv_sf_vc_i_se_u8mf2(p27_26, p24_20, p11_7, simm5, vl) \ argument
52 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 6, vl)
53 #define __riscv_sf_vc_i_se_u8m1(p27_26, p24_20, p11_7, simm5, vl) \ argument
54 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 0, vl)
55 #define __riscv_sf_vc_i_se_u8m2(p27_26, p24_20, p11_7, simm5, vl) \ argument
56 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 1, vl)
57 #define __riscv_sf_vc_i_se_u8m4(p27_26, p24_20, p11_7, simm5, vl) \ argument
58 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 2, vl)
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXqci.td487 (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2),
500 (ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2),
511 (ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3),
522 (ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2),
556 (ins GPRNoX0:$rd, GPRNoX0:$rs1, InTyRs2:$rs2, simm5:$simm),
849 (ins GPRNoX0:$rd, simm5:$imm5, uimm5_plus1:$width,
959 def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">;
960 def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">;
961 def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">;
962 def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">;
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H A DRISCVInstrInfoXTHead.td216 (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
217 opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
218 bits<5> simm5;
222 let Inst{24-20} = simm5;
239 (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
240 opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
241 bits<5> simm5;
245 let Inst{24-20} = simm5;
842 def : Pat<(st (vt GPR:$rd), GPR:$rs1, (simm5shl2 simm5:$simm5, uimm2:$uimm2)),
843 (Inst GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2)>;
H A DRISCVInstrInfoXCV.td591 (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
594 (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
793 def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
794 (CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
795 def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
796 (CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
798 defm CC_SImm5_CV : SelectCC_GPR_riirr<GPR, simm5>;
801 : Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
803 (Select_GPR_Using_CC_SImm5_CV GPR:$lhs, simm5:$Constant,
H A DRISCVInstrInfoXSf.td111 !eq(TyRs1, simm5): 0b011);
203 defm I : CustomSiFiveVCIX<"i", VCIX_X, uimm5, uimm5, simm5>, Sched<[]>;
205 defm IV : CustomSiFiveVCIX<"iv", VCIX_XV, uimm5, VR, simm5>, Sched<[]>;
209 defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR, VR, simm5>, Sched<[]>;
213 defm IVW : CustomSiFiveVCIX<"ivw", VCIX_XVW, VR, VR, simm5>, Sched<[]>;
H A DRISCVInstrInfoVVLPatterns.td726 // Give explicit Complexity to prefer simm5/uimm5.
960 Operand ImmType = simm5>
1202 (splatpat_kind simm5:$rs2), cc,
1211 def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2),
1217 simm5:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,
2104 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)),
2108 vti.RegClass:$passthru, vti.RegClass:$rs1, simm5:$rs2,
2377 (SplatPat_simm5 simm5:$rs1),
2382 vti.RegClass:$passthru, vti.RegClass:$rs2, simm5:$rs1,
2402 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
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H A DRISCVInstrInfoVSDPatterns.td143 Operand ImmType = simm5>
319 splatpat_kind, simm5>;
892 def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)),
896 simm5:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
1140 def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1),
1144 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask VMV0:$vm), vti.AVL, vti.Log2SEW)>;
H A DRISCVInstrInfoVPseudos.td2469 m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;
2475 m.vrclass, simm5, m>;
2491 def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>,
2669 defm _VI : VPseudoBinaryM<simm5, m>;
2701 defm "" : VPseudoBinaryV_VI<simm5, m>,
2744 defm "" : VPseudoBinaryV_VI<simm5, m>,
2943 defm "" : VPseudoBinaryV_VI<simm5, m>,
3049 m.vrclass, simm5, m>,
5286 vti.RegClass, simm5>;
5317 vti.RegClass, vti.RegClass, simm5>;
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H A DRISCVInstrInfoV.td72 def simm5 : RISCVSImmLeafOp<5> {
526 class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
532 class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
538 class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
1346 (ins simm5:$imm), "vmv.v.i", "$vd, $imm">,
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrInfo.td357 def XVMAXI_B : LASX2RI5_XXI<0x76900000, simm5>;
358 def XVMAXI_H : LASX2RI5_XXI<0x76908000, simm5>;
359 def XVMAXI_W : LASX2RI5_XXI<0x76910000, simm5>;
360 def XVMAXI_D : LASX2RI5_XXI<0x76918000, simm5>;
374 def XVMINI_B : LASX2RI5_XXI<0x76920000, simm5>;
375 def XVMINI_H : LASX2RI5_XXI<0x76928000, simm5>;
376 def XVMINI_W : LASX2RI5_XXI<0x76930000, simm5>;
377 def XVMINI_D : LASX2RI5_XXI<0x76938000, simm5>;
848 def XVSEQI_B : LASX2RI5_XXI<0x76800000, simm5>;
849 def XVSEQI_H : LASX2RI5_XXI<0x76808000, simm5>;
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H A DLoongArchLSXInstrInfo.td565 def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>;
566 def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>;
567 def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>;
568 def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>;
582 def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>;
583 def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>;
584 def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>;
585 def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>;
1043 def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>;
1044 def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>;
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H A DLoongArchLBTInstrInfo.td25 def ADDU12I_W : ALU_2RI5<0x00290000, simm5>;
191 def ADDU12I_D : ALU_2RI5<0x00298000, simm5>;
H A DLoongArchInstrInfo.td310 def simm5 : Operand<GRLenVT> {
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrUAOSA.td32 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, simm5Op:$simm5),
33 !strconcat(OpcStr, "$cond $rs1, $simm5, $imm10")>;
H A DSparcInstrFormats.td132 bits<5> simm5;
146 let Inst{4-0} = simm5;
H A DSparcInstrAliases.td339 def : InstAlias<"cwb" # cond # " $rs1, $simm5, $imm",
340 (CWBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
348 def : InstAlias<"cxb" # cond # " $rs1, $simm5, $imm",
349 (CXBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
H A DSparcInstrInfo.td105 def simm5 : PatLeaf<(imm), [{ return isInt<5>(N->getSExtValue()); }]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td101 let MIOperandInfo = (ops ptr_sp_rc:$base, simm5:$offset);
H A DMipsInstrInfo.td644 // simm4 < uimm4 < simm5 < uimm5