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Searched refs:rtwn_bb_setbits (Results 1 – 16 of 16) sorted by relevance

/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_chan.c64 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00100000, 0); in r21a_bypass_ext_lna_2ghz()
65 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0); in r21a_bypass_ext_lna_2ghz()
66 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x07); in r21a_bypass_ext_lna_2ghz()
67 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x0700); in r21a_bypass_ext_lna_2ghz()
76 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, in r21a_set_band_2ghz()
80 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
82 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
87 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0, 0x00100000); in r21a_set_band_2ghz()
88 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0); in r21a_set_band_2ghz()
89 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0x05, 0x02); in r21a_set_band_2ghz()
[all …]
H A Dr21a_calib.c108 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); in r21a_iq_calib_sw()
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_chan.c209 rtwn_bb_setbits(sc, R12A_TX_PWR_TRAINING(chain), in r12a_tx_power_training()
404 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00); in r12a_fix_spur()
405 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); in r12a_fix_spur()
407 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800); in r12a_fix_spur()
413 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); in r12a_fix_spur()
414 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, in r12a_fix_spur()
419 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, in r12a_fix_spur()
423 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); in r12a_fix_spur()
424 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, in r12a_fix_spur()
434 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); in r12a_fix_spur()
[all …]
H A Dr12a_calib.c133 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); in r12a_save_bb_afe_vals()
146 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); in r12a_restore_bb_afe_vals()
159 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); in r12a_save_rf_vals()
173 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); in r12a_restore_rf_vals()
192 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); in r12a_iq_config_mac()
201 rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x03, 0x0c); in r12a_iq_config_mac()
224 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); in r12a_iq_calib_sw()
245 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); in r12a_iq_calib_sw()
252 rtwn_bb_setbits(sc, 0xc90, 0, 0x00000080); in r12a_iq_calib_sw()
253 rtwn_bb_setbits(sc, 0xcc4, 0, 0x20040000); in r12a_iq_calib_sw()
[all …]
H A Dr12a_rf.c64 rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0, 0x08); in r12a_rf_read()
69 rtwn_bb_setbits(sc, R12A_HSSI_PARAM2, in r12a_rf_read()
77 rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x08, 0); in r12a_rf_read()
90 rtwn_bb_setbits(sc, R12A_HSSI_PARAM2, in r12a_c_cut_rf_read()
H A Dr12a_init.c480 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); in r12a_init_antsel()
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_init.c151 rtwn_bb_setbits(sc, R92C_FPGA0_TXINFO, 0x03, 0x02); in r92c_init_bb_common()
152 rtwn_bb_setbits(sc, R92C_FPGA1_TXINFO, 0x300033, 0x200022); in r92c_init_bb_common()
153 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0xff000000, in r92c_init_bb_common()
155 rtwn_bb_setbits(sc, R92C_OFDM0_TRXPATHENA, 0xff, 0x23); in r92c_init_bb_common()
156 rtwn_bb_setbits(sc, R92C_OFDM0_AGCPARAM1, 0x30, 0x10); in r92c_init_bb_common()
158 rtwn_bb_setbits(sc, 0xe74, 0x0c000000, 0x08000000); in r92c_init_bb_common()
159 rtwn_bb_setbits(sc, 0xe78, 0x0c000000, 0x08000000); in r92c_init_bb_common()
160 rtwn_bb_setbits(sc, 0xe7c, 0x0c000000, 0x08000000); in r92c_init_bb_common()
161 rtwn_bb_setbits(sc, 0xe80, 0x0c000000, 0x08000000); in r92c_init_bb_common()
162 rtwn_bb_setbits(sc, 0xe88, 0x0c000000, 0x08000000); in r92c_init_bb_common()
[all …]
H A Dr92c_calib.c191 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000); in r92c_iq_calib_run()
195 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400); in r92c_iq_calib_run()
196 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0); in r92c_iq_calib_run()
197 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0); in r92c_iq_calib_run()
345 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg); in r92c_iq_calib_write_results()
346 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, in r92c_iq_calib_write_results()
353 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000, in r92c_iq_calib_write_results()
355 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000, in r92c_iq_calib_write_results()
357 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, in r92c_iq_calib_write_results()
363 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff, in r92c_iq_calib_write_results()
[all …]
H A Dr92c_chan.c321 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ); in r92c_set_bw40()
322 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ); in r92c_set_bw40()
325 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, in r92c_set_bw40()
328 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, in r92c_set_bw40()
331 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, in r92c_set_bw40()
334 rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE, in r92c_set_bw40()
349 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); in r92c_set_bw20()
350 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); in r92c_set_bw20()
352 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 0, in r92c_set_bw20()
386 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0), in r92c_set_gain()
[all …]
/freebsd/sys/dev/rtwn/rtl8192e/
H A Dr92e_chan.c195 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ); in r92e_set_bw40()
196 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ); in r92e_set_bw40()
204 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, in r92e_set_bw40()
207 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10); in r92e_set_bw40()
209 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, in r92e_set_bw40()
212 rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26); in r92e_set_bw40()
223 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); in r92e_set_bw20()
224 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); in r92e_set_bw20()
231 rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0); in r92e_set_bw20()
H A Dr92e_rf.c68 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), R92C_HSSI_PARAM2_READ_EDGE, 0); in r92e_rf_read()
70 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), 0, R92C_HSSI_PARAM2_READ_EDGE); in r92e_rf_read()
84 rtwn_bb_setbits(sc, 0x818, 0x20000, 0); in r92e_rf_write()
88 rtwn_bb_setbits(sc, 0x818, 0, 0x20000); in r92e_rf_write()
H A Dr92e_init.c178 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), in r92e_init_rf()
182 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), in r92e_init_rf()
186 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), in r92e_init_rf()
189 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), in r92e_init_rf()
206 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN); in r92e_init_rf()
207 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN); in r92e_init_rf()
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_calib.c208 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000); in r88e_iq_calib_run()
212 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400); in r88e_iq_calib_run()
213 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0); in r88e_iq_calib_run()
214 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0); in r88e_iq_calib_run()
324 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x3ff, reg); in r88e_iq_calib_write_results()
325 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, in r88e_iq_calib_write_results()
332 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(0), 0xf0000000, in r88e_iq_calib_write_results()
334 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x003f0000, in r88e_iq_calib_write_results()
336 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, in r88e_iq_calib_write_results()
342 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0x3ff, in r88e_iq_calib_write_results()
[all …]
H A Dr88e_chan.c162 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); in r88e_set_bw20()
163 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); in r88e_set_bw20()
174 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0), in r88e_set_gain()
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_calib.c326 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg); in r92ce_iq_calib_write_results()
327 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, in r92ce_iq_calib_write_results()
334 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000, in r92ce_iq_calib_write_results()
336 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000, in r92ce_iq_calib_write_results()
338 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, in r92ce_iq_calib_write_results()
344 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff, in r92ce_iq_calib_write_results()
346 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00, in r92ce_iq_calib_write_results()
350 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000, in r92ce_iq_calib_write_results()
353 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000, in r92ce_iq_calib_write_results()
/freebsd/sys/dev/rtwn/rtl8821a/usb/
H A Dr21au_dfs.c66 rtwn_bb_setbits(sc, 0x924, 0x00008000, 0); in r21au_dfs_radar_disable()
80 error = rtwn_bb_setbits(sc, 0x924, 0x00008000, 0); in r21au_dfs_radar_reset()
84 return (rtwn_bb_setbits(sc, 0x924, 0, 0x00008000)); in r21au_dfs_radar_reset()
97 RTWN_CHK(rtwn_bb_setbits(sc, 0x814, 0x3fffffff, 0x04cc4d10)); in r21au_dfs_radar_enable()
98 RTWN_CHK(rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0xff, 0x06)); in r21au_dfs_radar_enable()