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Searched refs:reg_offset (Results 1 – 25 of 31) sorted by relevance

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/freebsd/sys/arm/ti/clk/
H A Dti_clkctrl.c93 create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset,
118 uint32_t index, reg_offset, reg_address; in ti_clkctrl_attach() local
193 for (reg_offset = 0; reg_offset < reg[index+1]; reg_offset += sizeof(cell_t)) { in ti_clkctrl_attach()
194 err = create_clkctrl(sc, reg, index, reg_offset, parent_offset, in ti_clkctrl_attach()
204 reg_address = reg[index] + reg_offset-reg[0]; in ti_clkctrl_attach()
209 err = create_clkctrl(sc, reg, index, reg_offset, in ti_clkctrl_attach()
216 reg_address = reg[index] + reg_offset - reg[0]; in ti_clkctrl_attach()
219 err = create_clkctrl(sc, reg, index, reg_offset, in ti_clkctrl_attach()
281 create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, in create_clkctrl() argument
299 def.clkdef.id = reg[index] + reg_offset - reg[0] + special_gdbclk_reg; in create_clkctrl()
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/freebsd/sys/arm64/qoriq/clk/
H A Dls1028a_flexspi_clk.c55 uint64_t reg_offset; member
153 sc->reg_offset = (uint64_t)cells[0]; in ls1028a_flexspi_clk_attach()
155 sc->reg_offset = (sc->reg_offset << 32) | (uint64_t)cells[1]; in ls1028a_flexspi_clk_attach()
164 if (sc->reg_offset >> 32UL) { in ls1028a_flexspi_clk_attach()
199 sc->clk_def.offset = (uint32_t)sc->reg_offset; in ls1028a_flexspi_clk_attach()
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_fw_funcs.c1024 u32 ctrl, inc_val, reg_offset; in ecore_init_nig_lb_rl() local
1062 for (tc = 0, reg_offset = 0; tc < NUM_OF_PHYS_TCS; tc++, reg_offset += 4) { in ecore_init_nig_lb_rl()
1065 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl); in ecore_init_nig_lb_rl()
1072 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 + reg_offset, NIG_RL_PERIOD_CLK_25M); in ecore_init_nig_lb_rl()
1074 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 + reg_offset, inc_val); in ecore_init_nig_lb_rl()
1075 …ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 + reg_offset, NIG_RL_MAX_VAL(inc_val, r… in ecore_init_nig_lb_rl()
1079 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl); in ecore_init_nig_lb_rl()
1187 u32 active_port_blocks, reg_offset = 0; in ecore_init_brb_ram() local
1223 for (tc = 0; tc < NUM_OF_TCS; tc++, reg_offset += 4) { in ecore_init_brb_ram()
1234 ecore_wr(p_hwfn, p_ptt, BRB_REG_TC_GUARANTIED_0 + reg_offset, tc_guaranteed_blocks); in ecore_init_brb_ram()
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H A Decore_dbg_fw_funcs.c2454 u32 reg_offset = constraint_id * BYTES_IN_DWORD; in ecore_bus_set_constraint() local
2460 reg_offset += curr_trigger_state * TRIGGER_SETS_PER_STATE * MAX_CONSTRAINTS * BYTES_IN_DWORD; in ecore_bus_set_constraint()
2463 …? DBG_REG_FILTER_CNSTR_OPRTN_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0) + reg_offset, hw_op_val); in ecore_bus_set_constraint()
2464 …er ? DBG_REG_FILTER_CNSTR_DATA_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0) + reg_offset, data_val); in ecore_bus_set_constraint()
2465 …G_FILTER_CNSTR_DATA_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0) + reg_offset, data_mask); in ecore_bus_set_constraint()
2466 …? DBG_REG_FILTER_CNSTR_FRAME_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0) + reg_offset, frame_bit); in ecore_bus_set_constraint()
2467 …ILTER_CNSTR_FRAME_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0) + reg_offset, frame_mask); in ecore_bus_set_constraint()
2468 …_REG_FILTER_CNSTR_OFFSET_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0) + reg_offset, dword_offset); in ecore_bus_set_constraint()
2469 …ter ? DBG_REG_FILTER_CNSTR_RANGE_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0) + reg_offset, range); in ecore_bus_set_constraint()
2470 …BG_REG_FILTER_CNSTR_CYCLIC_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0) + reg_offset, cyclic_bit); in ecore_bus_set_constraint()
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H A Decore_cxt.c2398 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; in ecore_cxt_dynamic_ilt_alloc() local
2497 reg_offset = PSWRQ2_REG_ILT_MEMORY + in ecore_cxt_dynamic_ilt_alloc()
2508 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), in ecore_cxt_dynamic_ilt_alloc()
2551 u32 reg_offset, elem_size, hw_p_size, elems_per_p; in ecore_cxt_free_ilt_range() local
2612 reg_offset = PSWRQ2_REG_ILT_MEMORY + in ecore_cxt_free_ilt_range()
2621 reg_offset, in ecore_cxt_free_ilt_range()
H A Decore_hsi_debug_tools.h526 …u16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk… member
/freebsd/sys/contrib/dev/athk/
H A Dath.h131 unsigned int (*read)(void *, u32 reg_offset);
133 void (*write)(void *, u32 val, u32 reg_offset);
136 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dsnoc.c76 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
81 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
86 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
91 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
96 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
101 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
106 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
111 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
116 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
121 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
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H A Dqmi.h68 __le16 reg_offset; member
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_mac.c42 u32 val, reg_offset; in mt792x_mac_set_timeing() local
58 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt792x_mac_set_timeing()
61 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset); in mt792x_mac_set_timeing()
62 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset); in mt792x_mac_set_timeing()
/freebsd/contrib/llvm-project/lldb/source/Target/
H A DDynamicRegisterInfo.cpp644 uint32_t reg_offset = 0; in ConfigureOffsets()
648 m_regs[regnum_pair.second].byte_offset = reg_offset; in ConfigureOffsets()
650 reg_offset = m_regs[regnum_pair.second].byte_offset + in ConfigureOffsets()
675 reg_offset = reg.byte_offset + reg.byte_size; in ConfigureOffsets()
676 if (m_reg_data_byte_size < reg_offset)
677 m_reg_data_byte_size = reg_offset; in IsReconfigurable()
640 uint32_t reg_offset = 0; ConfigureOffsets() local
/freebsd/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DDWARFLocationExpression.h31 uint16_t reg_offset; member
H A DDWARFLocationExpression.cpp280 : std::optional<int32_t>(loc.reg_offset); in MakeEnregisteredLocationExpressionForComposite()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/NetBSD/
H A DNativeRegisterContextNetBSD_x86_64.h80 uint8_t *GetOffsetRegSetData(RegSetKind set, size_t reg_offset);
H A DNativeRegisterContextNetBSD_x86_64.cpp602 size_t reg_offset) { in GetOffsetRegSetData() argument
619 assert(reg_offset >= m_regset_offsets[set]); in GetOffsetRegSetData()
620 return base + (reg_offset - m_regset_offsets[set]); in GetOffsetRegSetData()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/FreeBSD/
H A DNativeRegisterContextFreeBSD_x86_64.h83 uint8_t *GetOffsetRegSetData(RegSetKind set, size_t reg_offset);
H A DNativeRegisterContextFreeBSD_x86_64.cpp612 size_t reg_offset) { in GetOffsetRegSetData() argument
629 assert(reg_offset >= m_regset_offsets[set]); in GetOffsetRegSetData()
630 return base + (reg_offset - m_regset_offsets[set]); in GetOffsetRegSetData()
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie.h955 unsigned int reg_offset);
971 unsigned int reg_offset,
/freebsd/sys/dev/irdma/
H A Dicrdma_hw.c275 irdma_check_tc_has_pfc(struct irdma_sc_vsi *vsi, u64 reg_offset, u16 traffic_class) in irdma_check_tc_has_pfc() argument
280 value = rd32(vsi->dev->hw, reg_offset); in irdma_check_tc_has_pfc()
/freebsd/usr.sbin/bhyve/
H A Dpci_hda.c177 uint8_t reg_offset);
882 hda_get_stream_by_offsets(uint32_t offset, uint8_t reg_offset) in hda_get_stream_by_offsets() argument
884 uint8_t stream_ind = (offset - reg_offset) >> 5; in hda_get_stream_by_offsets()
/freebsd/sys/dev/e1000/
H A De1000_82575.c2040 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2044 reg_offset = E1000_DTXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2048 reg_offset = E1000_TXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2054 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2066 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.c145 u32 val, reg_offset; in mt7615_mac_set_timing() local
178 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7615_mac_set_timing()
180 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); in mt7615_mac_set_timing()
181 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); in mt7615_mac_set_timing()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.c52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7603_mac_set_timing() local
67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); in mt7603_mac_set_timing()
68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); in mt7603_mac_set_timing()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmac.c1455 u32 reg_offset; in mt7996_mac_set_coverage_class() local
1475 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7996_mac_set_coverage_class()
1478 mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset); in mt7996_mac_set_coverage_class()
1479 mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset); in mt7996_mac_set_coverage_class()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmac.c1187 u32 val, reg_offset; in mt7915_mac_set_timing() local
1208 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7915_mac_set_timing()
1223 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); in mt7915_mac_set_timing()
1224 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); in mt7915_mac_set_timing()

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