1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2014 Broadcom Corporation
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/firmware.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/bcma/bcma.h>
14 #include <linux/sched.h>
15 #include <linux/sched/signal.h>
16 #include <linux/kthread.h>
17 #include <linux/io.h>
18 #include <linux/random.h>
19 #include <linux/unaligned.h>
20
21 #include <soc.h>
22 #include <chipcommon.h>
23 #include <brcmu_utils.h>
24 #include <brcmu_wifi.h>
25 #include <brcm_hw_ids.h>
26
27 /* Custom brcmf_err() that takes bus arg and passes it further */
28 #define brcmf_err(bus, fmt, ...) \
29 do { \
30 if (IS_ENABLED(CONFIG_BRCMDBG) || \
31 IS_ENABLED(CONFIG_BRCM_TRACING) || \
32 net_ratelimit()) \
33 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \
34 } while (0)
35
36 #include "debug.h"
37 #include "bus.h"
38 #include "commonring.h"
39 #include "msgbuf.h"
40 #include "pcie.h"
41 #include "firmware.h"
42 #include "chip.h"
43 #include "core.h"
44 #include "common.h"
45
46
47 enum brcmf_pcie_state {
48 BRCMFMAC_PCIE_STATE_DOWN,
49 BRCMFMAC_PCIE_STATE_UP
50 };
51
52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
61 BRCMF_FW_DEF(4359C, "brcmfmac4359c-pcie");
62 BRCMF_FW_CLM_DEF(4364B2, "brcmfmac4364b2-pcie");
63 BRCMF_FW_CLM_DEF(4364B3, "brcmfmac4364b3-pcie");
64 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie");
65 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie");
66 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
67 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
68 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
69 BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie");
70 BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
71 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
72 BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
73 BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
74 BRCMF_FW_CLM_DEF(54591, "brcmfmac54591-pcie");
75
76 /* firmware config files */
77 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
78 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
79
80 /* per-board firmware binaries */
81 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin");
82 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob");
83 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txcap_blob");
84
85 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
86 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
87 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
88 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
89 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
90 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
91 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355),
92 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x00002000, 54591),
93 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */
94 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
95 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
96 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
97 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
98 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
99 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0x000001FF, 4359),
100 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFE00, 4359C),
101 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0x0000000F, 4364B2), /* 3 */
102 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFF0, 4364B3), /* 4 */
103 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
104 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
105 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
106 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
107 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
108 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
109 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
110 BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752),
111 BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
112 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
113 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
114 BRCMF_FW_ENTRY(BRCM_CC_4387_CHIP_ID, 0xFFFFFFFF, 4387C2), /* revision ID 7 */
115 };
116
117 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */
118
119 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
120
121 /* backplane addres space accessed by BAR0 */
122 #define BRCMF_PCIE_BAR0_WINDOW 0x80
123 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
124 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
125
126 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
127 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
128
129 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
130 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
131
132 #define BRCMF_PCIE_REG_INTSTATUS 0x90
133 #define BRCMF_PCIE_REG_INTMASK 0x94
134 #define BRCMF_PCIE_REG_SBMBX 0x98
135
136 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
137
138 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
139 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
140 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
141 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
142 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
143 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140
144 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144
145
146 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14
147 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30
148 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34
149 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20
150 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24
151
152 #define BRCMF_PCIE2_INTA 0x01
153 #define BRCMF_PCIE2_INTB 0x02
154
155 #define BRCMF_PCIE_INT_0 0x01
156 #define BRCMF_PCIE_INT_1 0x02
157 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
158 BRCMF_PCIE_INT_1)
159
160 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100
161 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200
162 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
163 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
164 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
165 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
166 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
167 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
168 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
169 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
170
171 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \
172 BRCMF_PCIE_MB_INT_FN0_1)
173 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
174 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
175 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
176 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
177 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
178 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
179 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
180 BRCMF_PCIE_MB_INT_D2H3_DB1)
181
182 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1
183 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2
184 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4
185 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8
186 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10
187 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20
188 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40
189 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80
190 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100
191 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200
192 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400
193 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800
194 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000
195 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000
196 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000
197 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000
198
199 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \
200 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \
201 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \
202 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \
203 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \
204 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \
205 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \
206 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \
207 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \
208 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \
209 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \
210 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \
211 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \
212 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \
213 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \
214 BRCMF_PCIE_64_MB_INT_D2H7_DB1)
215
216 #define BRCMF_PCIE_SHARED_VERSION_7 7
217 #define BRCMF_PCIE_MIN_SHARED_VERSION 5
218 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7
219 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
220 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
221 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
222 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000
223
224 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
225 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
226
227 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
228 #define BRCMF_SHARED_RING_BASE_OFFSET 52
229 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
230 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
231 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
232 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
233 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
234 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
235 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
236 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
237 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
238
239 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
240 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
241 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4
242 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8
243
244 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
245 #define BRCMF_RING_MAX_ITEM_OFFSET 4
246 #define BRCMF_RING_LEN_ITEMS_OFFSET 6
247 #define BRCMF_RING_MEM_SZ 16
248 #define BRCMF_RING_STATE_SZ 8
249
250 #define BRCMF_DEF_MAX_RXBUFPOST 255
251
252 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8
253 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
254 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
255
256 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
257 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
258
259 #define BRCMF_D2H_DEV_D3_ACK 0x00000001
260 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
261 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
262 #define BRCMF_D2H_DEV_FWHALT 0x10000000
263
264 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001
265 #define BRCMF_H2D_HOST_DS_ACK 0x00000002
266 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
267 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010
268
269 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000)
270
271 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
272 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
273 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
274 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
275 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
276 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
277 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
278 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
279 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
280 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
281 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
282 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
283 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
284
285 /* Magic number at a magic location to find RAM size */
286 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */
287 #define BRCMF_RAMSIZE_OFFSET 0x6c
288
289
290 struct brcmf_pcie_console {
291 u32 base_addr;
292 u32 buf_addr;
293 u32 bufsize;
294 u32 read_idx;
295 u8 log_str[256];
296 u8 log_idx;
297 };
298
299 struct brcmf_pcie_shared_info {
300 u32 tcm_base_address;
301 u32 flags;
302 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
303 struct brcmf_pcie_ringbuf *flowrings;
304 u16 max_rxbufpost;
305 u16 max_flowrings;
306 u16 max_submissionrings;
307 u16 max_completionrings;
308 u32 rx_dataoffset;
309 u32 htod_mb_data_addr;
310 u32 dtoh_mb_data_addr;
311 u32 ring_info_addr;
312 struct brcmf_pcie_console console;
313 void *scratch;
314 dma_addr_t scratch_dmahandle;
315 void *ringupd;
316 dma_addr_t ringupd_dmahandle;
317 u8 version;
318 };
319
320 #define BRCMF_OTP_MAX_PARAM_LEN 16
321
322 struct brcmf_otp_params {
323 char module[BRCMF_OTP_MAX_PARAM_LEN];
324 char vendor[BRCMF_OTP_MAX_PARAM_LEN];
325 char version[BRCMF_OTP_MAX_PARAM_LEN];
326 bool valid;
327 };
328
329 struct brcmf_pciedev_info {
330 enum brcmf_pcie_state state;
331 bool in_irq;
332 struct pci_dev *pdev;
333 char fw_name[BRCMF_FW_NAME_LEN];
334 char nvram_name[BRCMF_FW_NAME_LEN];
335 char clm_name[BRCMF_FW_NAME_LEN];
336 char txcap_name[BRCMF_FW_NAME_LEN];
337 const struct firmware *clm_fw;
338 const struct firmware *txcap_fw;
339 const struct brcmf_pcie_reginfo *reginfo;
340 void __iomem *regs;
341 void __iomem *tcm;
342 u32 ram_base;
343 u32 ram_size;
344 struct brcmf_chip *ci;
345 u32 coreid;
346 struct brcmf_pcie_shared_info shared;
347 wait_queue_head_t mbdata_resp_wait;
348 bool mbdata_completed;
349 bool irq_allocated;
350 bool wowl_enabled;
351 u8 dma_idx_sz;
352 void *idxbuf;
353 u32 idxbuf_sz;
354 dma_addr_t idxbuf_dmahandle;
355 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
356 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
357 u16 value);
358 struct brcmf_mp_device *settings;
359 struct brcmf_otp_params otp;
360 bool fwseed;
361 #ifdef DEBUG
362 u32 console_interval;
363 bool console_active;
364 struct timer_list timer;
365 #endif
366 };
367
368 struct brcmf_pcie_ringbuf {
369 struct brcmf_commonring commonring;
370 dma_addr_t dma_handle;
371 u32 w_idx_addr;
372 u32 r_idx_addr;
373 struct brcmf_pciedev_info *devinfo;
374 u8 id;
375 };
376
377 /**
378 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
379 *
380 * @ringmem: dongle memory pointer to ring memory location
381 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
382 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
383 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
384 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
385 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
386 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
387 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
388 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
389 * @max_flowrings: maximum number of tx flow rings supported.
390 * @max_submissionrings: maximum number of submission rings(h2d) supported.
391 * @max_completionrings: maximum number of completion rings(d2h) supported.
392 */
393 struct brcmf_pcie_dhi_ringinfo {
394 __le32 ringmem;
395 __le32 h2d_w_idx_ptr;
396 __le32 h2d_r_idx_ptr;
397 __le32 d2h_w_idx_ptr;
398 __le32 d2h_r_idx_ptr;
399 struct msgbuf_buf_addr h2d_w_idx_hostaddr;
400 struct msgbuf_buf_addr h2d_r_idx_hostaddr;
401 struct msgbuf_buf_addr d2h_w_idx_hostaddr;
402 struct msgbuf_buf_addr d2h_r_idx_hostaddr;
403 __le16 max_flowrings;
404 __le16 max_submissionrings;
405 __le16 max_completionrings;
406 };
407
408 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
409 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
410 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
411 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
412 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
413 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
414 };
415
416 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
417 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
418 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
419 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
420 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
421 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
422 };
423
424 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
425 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
426 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
427 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
428 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
429 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
430 };
431
432 struct brcmf_pcie_reginfo {
433 u32 intmask;
434 u32 mailboxint;
435 u32 mailboxmask;
436 u32 h2d_mailbox_0;
437 u32 h2d_mailbox_1;
438 u32 int_d2h_db;
439 u32 int_fn0;
440 };
441
442 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = {
443 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK,
444 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT,
445 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
446 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0,
447 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1,
448 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB,
449 .int_fn0 = BRCMF_PCIE_MB_INT_FN0,
450 };
451
452 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = {
453 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK,
454 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT,
455 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK,
456 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0,
457 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1,
458 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB,
459 .int_fn0 = 0,
460 };
461
462 static void brcmf_pcie_setup(struct device *dev, int ret,
463 struct brcmf_fw_request *fwreq);
464 static struct brcmf_fw_request *
465 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
466 static void
467 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active);
468 static void brcmf_pcie_debugfs_create(struct device *dev);
469
470 #if defined(__FreeBSD__)
471 #define VPAA(_x, _a) (void __iomem *)((uintptr_t)(_x) + (_a))
472 #endif
473
474 static u16
brcmf_pcie_read_reg16(struct brcmf_pciedev_info * devinfo,u32 reg_offset)475 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
476 {
477 #if defined(__linux__)
478 void __iomem *address = devinfo->regs + reg_offset;
479 #elif defined(__FreeBSD__)
480 void __iomem *address = VPAA(devinfo->regs, reg_offset);
481 #endif
482
483 return ioread16(address);
484 }
485
486 static u32
brcmf_pcie_read_reg32(struct brcmf_pciedev_info * devinfo,u32 reg_offset)487 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
488 {
489 #if defined(__linux__)
490 void __iomem *address = devinfo->regs + reg_offset;
491 #elif defined(__FreeBSD__)
492 void __iomem *address = VPAA(devinfo->regs, reg_offset);
493 #endif
494
495 return (ioread32(address));
496 }
497
498
499 static void
brcmf_pcie_write_reg32(struct brcmf_pciedev_info * devinfo,u32 reg_offset,u32 value)500 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
501 u32 value)
502 {
503 #if defined(__linux__)
504 void __iomem *address = devinfo->regs + reg_offset;
505 #elif defined(__FreeBSD__)
506 void __iomem *address = VPAA(devinfo->regs, reg_offset);
507 #endif
508
509 iowrite32(value, address);
510 }
511
512
513 static u8
brcmf_pcie_read_tcm8(struct brcmf_pciedev_info * devinfo,u32 mem_offset)514 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
515 {
516 #if defined(__linux__)
517 void __iomem *address = devinfo->tcm + mem_offset;
518 #elif defined(__FreeBSD__)
519 void __iomem *address = VPAA(devinfo->tcm, mem_offset);
520 #endif
521
522 return (ioread8(address));
523 }
524
525
526 static u16
brcmf_pcie_read_tcm16(struct brcmf_pciedev_info * devinfo,u32 mem_offset)527 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
528 {
529 #if defined(__linux__)
530 void __iomem *address = devinfo->tcm + mem_offset;
531 #elif defined(__FreeBSD__)
532 void __iomem *address = VPAA(devinfo->tcm, mem_offset);
533 #endif
534
535 return (ioread16(address));
536 }
537
538
539 static void
brcmf_pcie_write_tcm16(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u16 value)540 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
541 u16 value)
542 {
543 #if defined(__linux__)
544 void __iomem *address = devinfo->tcm + mem_offset;
545 #elif defined(__FreeBSD__)
546 void __iomem *address = VPAA(devinfo->tcm, mem_offset);
547 #endif
548
549 iowrite16(value, address);
550 }
551
552
553 static u16
brcmf_pcie_read_idx(struct brcmf_pciedev_info * devinfo,u32 mem_offset)554 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
555 {
556 #if defined(__linux__)
557 u16 *address = devinfo->idxbuf + mem_offset;
558 #elif defined(__FreeBSD__)
559 u16 *address = (void *)((uintptr_t)devinfo->idxbuf + mem_offset);
560 #endif
561
562 return (*(address));
563 }
564
565
566 static void
brcmf_pcie_write_idx(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u16 value)567 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
568 u16 value)
569 {
570 #if defined(__linux__)
571 u16 *address = devinfo->idxbuf + mem_offset;
572 #elif defined(__FreeBSD__)
573 u16 *address = (void *)((uintptr_t)devinfo->idxbuf + mem_offset);
574 #endif
575
576 *(address) = value;
577 }
578
579
580 static u32
brcmf_pcie_read_tcm32(struct brcmf_pciedev_info * devinfo,u32 mem_offset)581 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
582 {
583 #if defined(__linux__)
584 void __iomem *address = devinfo->tcm + mem_offset;
585 #elif defined(__FreeBSD__)
586 void __iomem *address = VPAA(devinfo->tcm, mem_offset);
587 #endif
588
589 return (ioread32(address));
590 }
591
592
593 static void
brcmf_pcie_write_tcm32(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u32 value)594 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
595 u32 value)
596 {
597 #if defined(__linux__)
598 void __iomem *address = devinfo->tcm + mem_offset;
599 #elif defined(__FreeBSD__)
600 void __iomem *address = VPAA(devinfo->tcm, mem_offset);
601 #endif
602
603 iowrite32(value, address);
604 }
605
606
607 static u32
brcmf_pcie_read_ram32(struct brcmf_pciedev_info * devinfo,u32 mem_offset)608 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
609 {
610 #if defined(__linux__)
611 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
612 #elif defined(__FreeBSD__)
613 void __iomem *addr = VPAA(devinfo->tcm, devinfo->ci->rambase + mem_offset);
614 #endif
615
616 return (ioread32(addr));
617 }
618
619
620 static void
brcmf_pcie_write_ram32(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u32 value)621 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
622 u32 value)
623 {
624 #if defined(__linux__)
625 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
626 #elif defined(__FreeBSD__)
627 void __iomem *addr = VPAA(devinfo->tcm, devinfo->ci->rambase + mem_offset);
628 #endif
629
630 iowrite32(value, addr);
631 }
632
633
634 static void
brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info * devinfo,u32 mem_offset,void * dstaddr,u32 len)635 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
636 void *dstaddr, u32 len)
637 {
638 #if defined(__linux__)
639 void __iomem *address = devinfo->tcm + mem_offset;
640 #elif defined(__FreeBSD__)
641 u8 __iomem *address = (void *)((uintptr_t)devinfo->tcm + mem_offset);
642 #endif
643 __le32 *dst32;
644 __le16 *dst16;
645 u8 *dst8;
646
647 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
648 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
649 dst8 = (u8 *)dstaddr;
650 while (len) {
651 *dst8 = ioread8(address);
652 address++;
653 dst8++;
654 len--;
655 }
656 } else {
657 len = len / 2;
658 dst16 = (__le16 *)dstaddr;
659 while (len) {
660 *dst16 = cpu_to_le16(ioread16(address));
661 address += 2;
662 dst16++;
663 len--;
664 }
665 }
666 } else {
667 len = len / 4;
668 dst32 = (__le32 *)dstaddr;
669 while (len) {
670 *dst32 = cpu_to_le32(ioread32(address));
671 address += 4;
672 dst32++;
673 len--;
674 }
675 }
676 }
677
678
679 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \
680 CHIPCREGOFFS(reg))
681 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
682 CHIPCREGOFFS(reg), value)
683
684
685 static void
brcmf_pcie_select_core(struct brcmf_pciedev_info * devinfo,u16 coreid)686 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
687 {
688 const struct pci_dev *pdev = devinfo->pdev;
689 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
690 struct brcmf_core *core;
691 u32 bar0_win;
692
693 core = brcmf_chip_get_core(devinfo->ci, coreid);
694 if (core) {
695 bar0_win = core->base;
696 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
697 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
698 &bar0_win) == 0) {
699 if (bar0_win != core->base) {
700 bar0_win = core->base;
701 pci_write_config_dword(pdev,
702 BRCMF_PCIE_BAR0_WINDOW,
703 bar0_win);
704 }
705 }
706 } else {
707 brcmf_err(bus, "Unsupported core selected %x\n", coreid);
708 }
709 }
710
711
brcmf_pcie_reset_device(struct brcmf_pciedev_info * devinfo)712 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
713 {
714 struct brcmf_core *core;
715 static const u16 cfg_offset[] = {
716 BRCMF_PCIE_CFGREG_STATUS_CMD,
717 BRCMF_PCIE_CFGREG_PM_CSR,
718 BRCMF_PCIE_CFGREG_MSI_CAP,
719 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
720 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
721 BRCMF_PCIE_CFGREG_MSI_DATA,
722 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
723 BRCMF_PCIE_CFGREG_RBAR_CTRL,
724 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
725 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
726 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG
727 };
728 u32 i;
729 u32 val;
730 u32 lsc;
731
732 if (!devinfo->ci)
733 return;
734
735 /* Disable ASPM */
736 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
737 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
738 &lsc);
739 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
740 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
741 val);
742
743 /* Watchdog reset */
744 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
745 WRITECC32(devinfo, watchdog, 4);
746 #if defined(__linux__)
747 msleep(100);
748 #elif defined(__FreeBSD__)
749 linux_msleep(100);
750 #endif
751
752 /* Restore ASPM */
753 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
754 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
755 lsc);
756
757 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
758 if (core->rev <= 13) {
759 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
760 brcmf_pcie_write_reg32(devinfo,
761 BRCMF_PCIE_PCIE2REG_CONFIGADDR,
762 cfg_offset[i]);
763 val = brcmf_pcie_read_reg32(devinfo,
764 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
765 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
766 cfg_offset[i], val);
767 brcmf_pcie_write_reg32(devinfo,
768 BRCMF_PCIE_PCIE2REG_CONFIGDATA,
769 val);
770 }
771 }
772 }
773
774
brcmf_pcie_attach(struct brcmf_pciedev_info * devinfo)775 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
776 {
777 u32 config;
778
779 /* BAR1 window may not be sized properly */
780 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
781 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
782 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
783 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
784
785 device_wakeup_enable(&devinfo->pdev->dev);
786 }
787
788
brcmf_pcie_enter_download_state(struct brcmf_pciedev_info * devinfo)789 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
790 {
791 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
792 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
793 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
794 5);
795 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
796 0);
797 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
798 7);
799 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
800 0);
801 }
802 return 0;
803 }
804
805
brcmf_pcie_exit_download_state(struct brcmf_pciedev_info * devinfo,u32 resetintr)806 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
807 u32 resetintr)
808 {
809 struct brcmf_core *core;
810
811 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
812 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
813 brcmf_chip_resetcore(core, 0, 0, 0);
814 }
815
816 if (!brcmf_chip_set_active(devinfo->ci, resetintr))
817 return -EIO;
818 return 0;
819 }
820
821
822 static int
brcmf_pcie_send_mb_data(struct brcmf_pciedev_info * devinfo,u32 htod_mb_data)823 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
824 {
825 struct brcmf_pcie_shared_info *shared;
826 struct brcmf_core *core;
827 u32 addr;
828 u32 cur_htod_mb_data;
829 u32 i;
830
831 shared = &devinfo->shared;
832 addr = shared->htod_mb_data_addr;
833 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
834
835 if (cur_htod_mb_data != 0)
836 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
837 cur_htod_mb_data);
838
839 i = 0;
840 while (cur_htod_mb_data != 0) {
841 #if defined(__linux__)
842 msleep(10);
843 #elif defined(__FreeBSD__)
844 linux_msleep(10);
845 #endif
846 i++;
847 if (i > 100)
848 return -EIO;
849 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
850 }
851
852 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
853 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
854
855 /* Send mailbox interrupt twice as a hardware workaround */
856 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
857 if (core->rev <= 13)
858 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
859
860 return 0;
861 }
862
863
brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info * devinfo)864 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
865 {
866 struct brcmf_pcie_shared_info *shared;
867 u32 addr;
868 u32 dtoh_mb_data;
869
870 shared = &devinfo->shared;
871 addr = shared->dtoh_mb_data_addr;
872 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
873
874 if (!dtoh_mb_data)
875 return;
876
877 brcmf_pcie_write_tcm32(devinfo, addr, 0);
878
879 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
880 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
881 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
882 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
883 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
884 }
885 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
886 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
887 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
888 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
889 devinfo->mbdata_completed = true;
890 wake_up(&devinfo->mbdata_resp_wait);
891 }
892 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
893 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
894 brcmf_fw_crashed(&devinfo->pdev->dev);
895 }
896 }
897
898
brcmf_pcie_bus_console_init(struct brcmf_pciedev_info * devinfo)899 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
900 {
901 struct brcmf_pcie_shared_info *shared;
902 struct brcmf_pcie_console *console;
903 u32 addr;
904
905 shared = &devinfo->shared;
906 console = &shared->console;
907 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
908 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
909
910 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
911 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
912 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
913 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
914
915 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
916 console->base_addr, console->buf_addr, console->bufsize);
917 }
918
919 /**
920 * brcmf_pcie_bus_console_read - reads firmware messages
921 *
922 * @devinfo: pointer to the device data structure
923 * @error: specifies if error has occurred (prints messages unconditionally)
924 */
brcmf_pcie_bus_console_read(struct brcmf_pciedev_info * devinfo,bool error)925 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
926 bool error)
927 {
928 struct pci_dev *pdev = devinfo->pdev;
929 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
930 struct brcmf_pcie_console *console;
931 u32 addr;
932 u8 ch;
933 u32 newidx;
934
935 if (!error && !BRCMF_FWCON_ON())
936 return;
937
938 console = &devinfo->shared.console;
939 if (!console->base_addr)
940 return;
941 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
942 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
943 while (newidx != console->read_idx) {
944 addr = console->buf_addr + console->read_idx;
945 ch = brcmf_pcie_read_tcm8(devinfo, addr);
946 console->read_idx++;
947 if (console->read_idx == console->bufsize)
948 console->read_idx = 0;
949 if (ch == '\r')
950 continue;
951 console->log_str[console->log_idx] = ch;
952 console->log_idx++;
953 if ((ch != '\n') &&
954 (console->log_idx == (sizeof(console->log_str) - 2))) {
955 ch = '\n';
956 console->log_str[console->log_idx] = ch;
957 console->log_idx++;
958 }
959 if (ch == '\n') {
960 console->log_str[console->log_idx] = 0;
961 if (error)
962 __brcmf_err(bus, __func__, "CONSOLE: %s",
963 console->log_str);
964 else
965 pr_debug("CONSOLE: %s", console->log_str);
966 console->log_idx = 0;
967 }
968 }
969 }
970
971
brcmf_pcie_intr_disable(struct brcmf_pciedev_info * devinfo)972 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
973 {
974 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0);
975 }
976
977
brcmf_pcie_intr_enable(struct brcmf_pciedev_info * devinfo)978 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
979 {
980 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask,
981 devinfo->reginfo->int_d2h_db |
982 devinfo->reginfo->int_fn0);
983 }
984
brcmf_pcie_hostready(struct brcmf_pciedev_info * devinfo)985 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
986 {
987 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
988 brcmf_pcie_write_reg32(devinfo,
989 devinfo->reginfo->h2d_mailbox_1, 1);
990 }
991
brcmf_pcie_quick_check_isr(int irq,void * arg)992 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
993 {
994 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
995
996 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) {
997 brcmf_pcie_intr_disable(devinfo);
998 brcmf_dbg(PCIE, "Enter\n");
999 return IRQ_WAKE_THREAD;
1000 }
1001 return IRQ_NONE;
1002 }
1003
1004
brcmf_pcie_isr_thread(int irq,void * arg)1005 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
1006 {
1007 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
1008 u32 status;
1009
1010 devinfo->in_irq = true;
1011 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
1012 brcmf_dbg(PCIE, "Enter %x\n", status);
1013 if (status) {
1014 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint,
1015 status);
1016 if (status & devinfo->reginfo->int_fn0)
1017 brcmf_pcie_handle_mb_data(devinfo);
1018 if (status & devinfo->reginfo->int_d2h_db) {
1019 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
1020 brcmf_proto_msgbuf_rx_trigger(
1021 &devinfo->pdev->dev);
1022 }
1023 }
1024 brcmf_pcie_bus_console_read(devinfo, false);
1025 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
1026 brcmf_pcie_intr_enable(devinfo);
1027 devinfo->in_irq = false;
1028 return IRQ_HANDLED;
1029 }
1030
1031
brcmf_pcie_request_irq(struct brcmf_pciedev_info * devinfo)1032 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
1033 {
1034 struct pci_dev *pdev = devinfo->pdev;
1035 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1036
1037 brcmf_pcie_intr_disable(devinfo);
1038
1039 brcmf_dbg(PCIE, "Enter\n");
1040
1041 pci_enable_msi(pdev);
1042 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
1043 brcmf_pcie_isr_thread, IRQF_SHARED,
1044 "brcmf_pcie_intr", devinfo)) {
1045 pci_disable_msi(pdev);
1046 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq);
1047 return -EIO;
1048 }
1049 devinfo->irq_allocated = true;
1050 return 0;
1051 }
1052
1053
brcmf_pcie_release_irq(struct brcmf_pciedev_info * devinfo)1054 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
1055 {
1056 struct pci_dev *pdev = devinfo->pdev;
1057 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1058 u32 status;
1059 u32 count;
1060
1061 if (!devinfo->irq_allocated)
1062 return;
1063
1064 brcmf_pcie_intr_disable(devinfo);
1065 free_irq(pdev->irq, devinfo);
1066 pci_disable_msi(pdev);
1067
1068 #if defined(__linux__)
1069 msleep(50);
1070 #elif defined(__FreeBSD__)
1071 linux_msleep(50);
1072 #endif
1073 count = 0;
1074 while ((devinfo->in_irq) && (count < 20)) {
1075 #if defined(__linux__)
1076 msleep(50);
1077 #elif defined(__FreeBSD__)
1078 linux_msleep(50);
1079 #endif
1080 count++;
1081 }
1082 if (devinfo->in_irq)
1083 brcmf_err(bus, "Still in IRQ (processing) !!!\n");
1084
1085 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
1086 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status);
1087
1088 devinfo->irq_allocated = false;
1089 }
1090
1091
brcmf_pcie_ring_mb_write_rptr(void * ctx)1092 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
1093 {
1094 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1095 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1096 struct brcmf_commonring *commonring = &ring->commonring;
1097
1098 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1099 return -EIO;
1100
1101 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1102 commonring->w_ptr, ring->id);
1103
1104 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
1105
1106 return 0;
1107 }
1108
1109
brcmf_pcie_ring_mb_write_wptr(void * ctx)1110 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
1111 {
1112 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1113 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1114 struct brcmf_commonring *commonring = &ring->commonring;
1115
1116 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1117 return -EIO;
1118
1119 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1120 commonring->r_ptr, ring->id);
1121
1122 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
1123
1124 return 0;
1125 }
1126
1127
brcmf_pcie_ring_mb_ring_bell(void * ctx)1128 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
1129 {
1130 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1131 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1132
1133 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1134 return -EIO;
1135
1136 brcmf_dbg(PCIE, "RING !\n");
1137 /* Any arbitrary value will do, lets use 1 */
1138 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1);
1139
1140 return 0;
1141 }
1142
1143
brcmf_pcie_ring_mb_update_rptr(void * ctx)1144 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1145 {
1146 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1147 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1148 struct brcmf_commonring *commonring = &ring->commonring;
1149
1150 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1151 return -EIO;
1152
1153 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1154
1155 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1156 commonring->w_ptr, ring->id);
1157
1158 return 0;
1159 }
1160
1161
brcmf_pcie_ring_mb_update_wptr(void * ctx)1162 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1163 {
1164 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1165 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1166 struct brcmf_commonring *commonring = &ring->commonring;
1167
1168 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1169 return -EIO;
1170
1171 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1172
1173 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1174 commonring->r_ptr, ring->id);
1175
1176 return 0;
1177 }
1178
1179
1180 static void *
brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info * devinfo,u32 size,u32 tcm_dma_phys_addr,dma_addr_t * dma_handle)1181 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1182 u32 size, u32 tcm_dma_phys_addr,
1183 dma_addr_t *dma_handle)
1184 {
1185 void *ring;
1186 u64 address;
1187
1188 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1189 GFP_KERNEL);
1190 if (!ring)
1191 return NULL;
1192
1193 address = (u64)*dma_handle;
1194 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1195 address & 0xffffffff);
1196 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1197
1198 return (ring);
1199 }
1200
1201
1202 static struct brcmf_pcie_ringbuf *
brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info * devinfo,u32 ring_id,u32 tcm_ring_phys_addr)1203 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1204 u32 tcm_ring_phys_addr)
1205 {
1206 void *dma_buf;
1207 dma_addr_t dma_handle;
1208 struct brcmf_pcie_ringbuf *ring;
1209 u32 size;
1210 u32 addr;
1211 const u32 *ring_itemsize_array;
1212
1213 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
1214 ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
1215 else
1216 ring_itemsize_array = brcmf_ring_itemsize;
1217
1218 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
1219 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1220 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1221 &dma_handle);
1222 if (!dma_buf)
1223 return NULL;
1224
1225 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1226 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1227 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1228 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
1229
1230 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1231 if (!ring) {
1232 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1233 dma_handle);
1234 return NULL;
1235 }
1236 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1237 ring_itemsize_array[ring_id], dma_buf);
1238 ring->dma_handle = dma_handle;
1239 ring->devinfo = devinfo;
1240 brcmf_commonring_register_cb(&ring->commonring,
1241 brcmf_pcie_ring_mb_ring_bell,
1242 brcmf_pcie_ring_mb_update_rptr,
1243 brcmf_pcie_ring_mb_update_wptr,
1244 brcmf_pcie_ring_mb_write_rptr,
1245 brcmf_pcie_ring_mb_write_wptr, ring);
1246
1247 return (ring);
1248 }
1249
1250
brcmf_pcie_release_ringbuffer(struct device * dev,struct brcmf_pcie_ringbuf * ring)1251 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1252 struct brcmf_pcie_ringbuf *ring)
1253 {
1254 void *dma_buf;
1255 u32 size;
1256
1257 if (!ring)
1258 return;
1259
1260 dma_buf = ring->commonring.buf_addr;
1261 if (dma_buf) {
1262 size = ring->commonring.depth * ring->commonring.item_len;
1263 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1264 }
1265 kfree(ring);
1266 }
1267
1268
brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info * devinfo)1269 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1270 {
1271 u32 i;
1272
1273 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1274 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1275 devinfo->shared.commonrings[i]);
1276 devinfo->shared.commonrings[i] = NULL;
1277 }
1278 kfree(devinfo->shared.flowrings);
1279 devinfo->shared.flowrings = NULL;
1280 if (devinfo->idxbuf) {
1281 dma_free_coherent(&devinfo->pdev->dev,
1282 devinfo->idxbuf_sz,
1283 devinfo->idxbuf,
1284 devinfo->idxbuf_dmahandle);
1285 devinfo->idxbuf = NULL;
1286 }
1287 }
1288
1289
brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info * devinfo)1290 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1291 {
1292 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1293 struct brcmf_pcie_ringbuf *ring;
1294 struct brcmf_pcie_ringbuf *rings;
1295 u32 d2h_w_idx_ptr;
1296 u32 d2h_r_idx_ptr;
1297 u32 h2d_w_idx_ptr;
1298 u32 h2d_r_idx_ptr;
1299 u32 ring_mem_ptr;
1300 u32 i;
1301 u64 address;
1302 u32 bufsz;
1303 u8 idx_offset;
1304 struct brcmf_pcie_dhi_ringinfo ringinfo;
1305 u16 max_flowrings;
1306 u16 max_submissionrings;
1307 u16 max_completionrings;
1308
1309 #if defined(__linux__)
1310 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1311 #elif defined(__FreeBSD__)
1312 memcpy_fromio(&ringinfo, (void *)((uintptr_t)devinfo->tcm + devinfo->shared.ring_info_addr),
1313 #endif
1314 sizeof(ringinfo));
1315 if (devinfo->shared.version >= 6) {
1316 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1317 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1318 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1319 } else {
1320 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1321 max_flowrings = max_submissionrings -
1322 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1323 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1324 }
1325 if (max_flowrings > 512) {
1326 brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings);
1327 return -EIO;
1328 }
1329
1330 if (devinfo->dma_idx_sz != 0) {
1331 bufsz = (max_submissionrings + max_completionrings) *
1332 devinfo->dma_idx_sz * 2;
1333 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1334 &devinfo->idxbuf_dmahandle,
1335 GFP_KERNEL);
1336 if (!devinfo->idxbuf)
1337 devinfo->dma_idx_sz = 0;
1338 }
1339
1340 if (devinfo->dma_idx_sz == 0) {
1341 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1342 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1343 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1344 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1345 idx_offset = sizeof(u32);
1346 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1347 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1348 brcmf_dbg(PCIE, "Using TCM indices\n");
1349 } else {
1350 memset(devinfo->idxbuf, 0, bufsz);
1351 devinfo->idxbuf_sz = bufsz;
1352 idx_offset = devinfo->dma_idx_sz;
1353 devinfo->write_ptr = brcmf_pcie_write_idx;
1354 devinfo->read_ptr = brcmf_pcie_read_idx;
1355
1356 h2d_w_idx_ptr = 0;
1357 address = (u64)devinfo->idxbuf_dmahandle;
1358 ringinfo.h2d_w_idx_hostaddr.low_addr =
1359 cpu_to_le32(address & 0xffffffff);
1360 ringinfo.h2d_w_idx_hostaddr.high_addr =
1361 cpu_to_le32(address >> 32);
1362
1363 h2d_r_idx_ptr = h2d_w_idx_ptr +
1364 max_submissionrings * idx_offset;
1365 address += max_submissionrings * idx_offset;
1366 ringinfo.h2d_r_idx_hostaddr.low_addr =
1367 cpu_to_le32(address & 0xffffffff);
1368 ringinfo.h2d_r_idx_hostaddr.high_addr =
1369 cpu_to_le32(address >> 32);
1370
1371 d2h_w_idx_ptr = h2d_r_idx_ptr +
1372 max_submissionrings * idx_offset;
1373 address += max_submissionrings * idx_offset;
1374 ringinfo.d2h_w_idx_hostaddr.low_addr =
1375 cpu_to_le32(address & 0xffffffff);
1376 ringinfo.d2h_w_idx_hostaddr.high_addr =
1377 cpu_to_le32(address >> 32);
1378
1379 d2h_r_idx_ptr = d2h_w_idx_ptr +
1380 max_completionrings * idx_offset;
1381 address += max_completionrings * idx_offset;
1382 ringinfo.d2h_r_idx_hostaddr.low_addr =
1383 cpu_to_le32(address & 0xffffffff);
1384 ringinfo.d2h_r_idx_hostaddr.high_addr =
1385 cpu_to_le32(address >> 32);
1386
1387 #if defined(__linux__)
1388 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1389 #elif defined(__FreeBSD__)
1390 memcpy_toio((void *)((uintptr_t)devinfo->tcm + devinfo->shared.ring_info_addr),
1391 #endif
1392 &ringinfo, sizeof(ringinfo));
1393 brcmf_dbg(PCIE, "Using host memory indices\n");
1394 }
1395
1396 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1397
1398 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1399 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1400 if (!ring)
1401 goto fail;
1402 ring->w_idx_addr = h2d_w_idx_ptr;
1403 ring->r_idx_addr = h2d_r_idx_ptr;
1404 ring->id = i;
1405 devinfo->shared.commonrings[i] = ring;
1406
1407 h2d_w_idx_ptr += idx_offset;
1408 h2d_r_idx_ptr += idx_offset;
1409 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1410 }
1411
1412 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1413 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1414 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1415 if (!ring)
1416 goto fail;
1417 ring->w_idx_addr = d2h_w_idx_ptr;
1418 ring->r_idx_addr = d2h_r_idx_ptr;
1419 ring->id = i;
1420 devinfo->shared.commonrings[i] = ring;
1421
1422 d2h_w_idx_ptr += idx_offset;
1423 d2h_r_idx_ptr += idx_offset;
1424 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1425 }
1426
1427 devinfo->shared.max_flowrings = max_flowrings;
1428 devinfo->shared.max_submissionrings = max_submissionrings;
1429 devinfo->shared.max_completionrings = max_completionrings;
1430 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1431 if (!rings)
1432 goto fail;
1433
1434 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1435
1436 for (i = 0; i < max_flowrings; i++) {
1437 ring = &rings[i];
1438 ring->devinfo = devinfo;
1439 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1440 brcmf_commonring_register_cb(&ring->commonring,
1441 brcmf_pcie_ring_mb_ring_bell,
1442 brcmf_pcie_ring_mb_update_rptr,
1443 brcmf_pcie_ring_mb_update_wptr,
1444 brcmf_pcie_ring_mb_write_rptr,
1445 brcmf_pcie_ring_mb_write_wptr,
1446 ring);
1447 ring->w_idx_addr = h2d_w_idx_ptr;
1448 ring->r_idx_addr = h2d_r_idx_ptr;
1449 h2d_w_idx_ptr += idx_offset;
1450 h2d_r_idx_ptr += idx_offset;
1451 }
1452 devinfo->shared.flowrings = rings;
1453
1454 return 0;
1455
1456 fail:
1457 brcmf_err(bus, "Allocating ring buffers failed\n");
1458 brcmf_pcie_release_ringbuffers(devinfo);
1459 return -ENOMEM;
1460 }
1461
1462
1463 static void
brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info * devinfo)1464 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1465 {
1466 if (devinfo->shared.scratch)
1467 dma_free_coherent(&devinfo->pdev->dev,
1468 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1469 devinfo->shared.scratch,
1470 devinfo->shared.scratch_dmahandle);
1471 if (devinfo->shared.ringupd)
1472 dma_free_coherent(&devinfo->pdev->dev,
1473 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1474 devinfo->shared.ringupd,
1475 devinfo->shared.ringupd_dmahandle);
1476 }
1477
brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info * devinfo)1478 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1479 {
1480 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1481 u64 address;
1482 u32 addr;
1483
1484 devinfo->shared.scratch =
1485 dma_alloc_coherent(&devinfo->pdev->dev,
1486 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1487 &devinfo->shared.scratch_dmahandle,
1488 GFP_KERNEL);
1489 if (!devinfo->shared.scratch)
1490 goto fail;
1491
1492 addr = devinfo->shared.tcm_base_address +
1493 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1494 address = (u64)devinfo->shared.scratch_dmahandle;
1495 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1496 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1497 addr = devinfo->shared.tcm_base_address +
1498 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1499 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1500
1501 devinfo->shared.ringupd =
1502 dma_alloc_coherent(&devinfo->pdev->dev,
1503 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1504 &devinfo->shared.ringupd_dmahandle,
1505 GFP_KERNEL);
1506 if (!devinfo->shared.ringupd)
1507 goto fail;
1508
1509 addr = devinfo->shared.tcm_base_address +
1510 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1511 address = (u64)devinfo->shared.ringupd_dmahandle;
1512 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1513 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1514 addr = devinfo->shared.tcm_base_address +
1515 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1516 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1517 return 0;
1518
1519 fail:
1520 brcmf_err(bus, "Allocating scratch buffers failed\n");
1521 brcmf_pcie_release_scratchbuffers(devinfo);
1522 return -ENOMEM;
1523 }
1524
1525
brcmf_pcie_down(struct device * dev)1526 static void brcmf_pcie_down(struct device *dev)
1527 {
1528 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1529 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
1530 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1531
1532 brcmf_pcie_fwcon_timer(devinfo, false);
1533 }
1534
brcmf_pcie_preinit(struct device * dev)1535 static int brcmf_pcie_preinit(struct device *dev)
1536 {
1537 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1538 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1539
1540 brcmf_dbg(PCIE, "Enter\n");
1541
1542 brcmf_pcie_intr_enable(buspub->devinfo);
1543 brcmf_pcie_hostready(buspub->devinfo);
1544
1545 return 0;
1546 }
1547
brcmf_pcie_tx(struct device * dev,struct sk_buff * skb)1548 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1549 {
1550 return 0;
1551 }
1552
1553
brcmf_pcie_tx_ctlpkt(struct device * dev,unsigned char * msg,uint len)1554 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1555 uint len)
1556 {
1557 return 0;
1558 }
1559
1560
brcmf_pcie_rx_ctlpkt(struct device * dev,unsigned char * msg,uint len)1561 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1562 uint len)
1563 {
1564 return 0;
1565 }
1566
1567
brcmf_pcie_wowl_config(struct device * dev,bool enabled)1568 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1569 {
1570 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1571 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1572 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1573
1574 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1575 devinfo->wowl_enabled = enabled;
1576 }
1577
1578
brcmf_pcie_get_ramsize(struct device * dev)1579 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1580 {
1581 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1582 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1583 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1584
1585 return devinfo->ci->ramsize - devinfo->ci->srsize;
1586 }
1587
1588
brcmf_pcie_get_memdump(struct device * dev,void * data,size_t len)1589 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1590 {
1591 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1592 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1593 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1594
1595 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1596 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1597 return 0;
1598 }
1599
brcmf_pcie_get_blob(struct device * dev,const struct firmware ** fw,enum brcmf_blob_type type)1600 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw,
1601 enum brcmf_blob_type type)
1602 {
1603 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1604 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1605 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1606
1607 switch (type) {
1608 case BRCMF_BLOB_CLM:
1609 *fw = devinfo->clm_fw;
1610 devinfo->clm_fw = NULL;
1611 break;
1612 case BRCMF_BLOB_TXCAP:
1613 *fw = devinfo->txcap_fw;
1614 devinfo->txcap_fw = NULL;
1615 break;
1616 default:
1617 return -ENOENT;
1618 }
1619
1620 if (!*fw)
1621 return -ENOENT;
1622
1623 return 0;
1624 }
1625
brcmf_pcie_reset(struct device * dev)1626 static int brcmf_pcie_reset(struct device *dev)
1627 {
1628 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1629 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1630 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1631 struct brcmf_fw_request *fwreq;
1632 int err;
1633
1634 brcmf_pcie_intr_disable(devinfo);
1635
1636 brcmf_pcie_bus_console_read(devinfo, true);
1637
1638 brcmf_detach(dev);
1639
1640 brcmf_pcie_release_irq(devinfo);
1641 brcmf_pcie_release_scratchbuffers(devinfo);
1642 brcmf_pcie_release_ringbuffers(devinfo);
1643 brcmf_pcie_reset_device(devinfo);
1644
1645 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1646 if (!fwreq) {
1647 dev_err(dev, "Failed to prepare FW request\n");
1648 return -ENOMEM;
1649 }
1650
1651 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup);
1652 if (err) {
1653 dev_err(dev, "Failed to prepare FW request\n");
1654 kfree(fwreq);
1655 }
1656
1657 return err;
1658 }
1659
1660 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1661 .preinit = brcmf_pcie_preinit,
1662 .txdata = brcmf_pcie_tx,
1663 .stop = brcmf_pcie_down,
1664 .txctl = brcmf_pcie_tx_ctlpkt,
1665 .rxctl = brcmf_pcie_rx_ctlpkt,
1666 .wowl_config = brcmf_pcie_wowl_config,
1667 .get_ramsize = brcmf_pcie_get_ramsize,
1668 .get_memdump = brcmf_pcie_get_memdump,
1669 .get_blob = brcmf_pcie_get_blob,
1670 .reset = brcmf_pcie_reset,
1671 .debugfs_create = brcmf_pcie_debugfs_create,
1672 };
1673
1674
1675 static void
1676 #if defined(__linux__)
brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info * devinfo,u8 * data,u32 data_len)1677 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1678 #elif defined(__FreeBSD__)
1679 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, const u8 *data,
1680 #endif
1681 u32 data_len)
1682 {
1683 #if defined(__linux__)
1684 __le32 *field;
1685 #elif defined(__FreeBSD__)
1686 const __le32 *field;
1687 #endif
1688 u32 newsize;
1689
1690 if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1691 return;
1692
1693 #if defined(__linux__)
1694 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1695 #elif defined(__FreeBSD__)
1696 field = (const __le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1697 #endif
1698 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1699 return;
1700 field++;
1701 newsize = le32_to_cpup(field);
1702
1703 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1704 newsize);
1705 devinfo->ci->ramsize = newsize;
1706 }
1707
1708
1709 static int
brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info * devinfo,u32 sharedram_addr)1710 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1711 u32 sharedram_addr)
1712 {
1713 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1714 struct brcmf_pcie_shared_info *shared;
1715 u32 addr;
1716
1717 shared = &devinfo->shared;
1718 shared->tcm_base_address = sharedram_addr;
1719
1720 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1721 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1722 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1723 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1724 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1725 brcmf_err(bus, "Unsupported PCIE version %d\n",
1726 shared->version);
1727 return -EINVAL;
1728 }
1729
1730 /* check firmware support dma indicies */
1731 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1732 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1733 devinfo->dma_idx_sz = sizeof(u16);
1734 else
1735 devinfo->dma_idx_sz = sizeof(u32);
1736 }
1737
1738 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1739 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1740 if (shared->max_rxbufpost == 0)
1741 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1742
1743 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1744 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1745
1746 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1747 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1748
1749 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1750 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1751
1752 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1753 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1754
1755 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1756 shared->max_rxbufpost, shared->rx_dataoffset);
1757
1758 brcmf_pcie_bus_console_init(devinfo);
1759 brcmf_pcie_bus_console_read(devinfo, false);
1760
1761 return 0;
1762 }
1763
1764 struct brcmf_random_seed_footer {
1765 __le32 length;
1766 __le32 magic;
1767 };
1768
1769 #define BRCMF_RANDOM_SEED_MAGIC 0xfeedc0de
1770 #define BRCMF_RANDOM_SEED_LENGTH 0x100
1771
1772 static noinline_for_stack void
brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info * devinfo,u32 address)1773 brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info *devinfo, u32 address)
1774 {
1775 u8 randbuf[BRCMF_RANDOM_SEED_LENGTH];
1776
1777 get_random_bytes(randbuf, BRCMF_RANDOM_SEED_LENGTH);
1778 #if defined(__linux__)
1779 memcpy_toio(devinfo->tcm + address, randbuf, BRCMF_RANDOM_SEED_LENGTH);
1780 #elif defined(__FreeBSD__)
1781 memcpy_toio((void *)((uintptr_t)devinfo->tcm + address), randbuf, BRCMF_RANDOM_SEED_LENGTH);
1782 #endif
1783 }
1784
brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info * devinfo,const struct firmware * fw,void * nvram,u32 nvram_len)1785 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1786 const struct firmware *fw, void *nvram,
1787 u32 nvram_len)
1788 {
1789 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1790 u32 sharedram_addr;
1791 u32 sharedram_addr_written;
1792 u32 loop_counter;
1793 int err;
1794 u32 address;
1795 u32 resetintr;
1796
1797 brcmf_dbg(PCIE, "Halt ARM.\n");
1798 err = brcmf_pcie_enter_download_state(devinfo);
1799 if (err)
1800 return err;
1801
1802 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1803 #if defined(__linux__)
1804 memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1805 (void *)fw->data, fw->size);
1806 #elif defined(__FreeBSD__)
1807 memcpy_toio((void *)((uintptr_t)devinfo->tcm + devinfo->ci->rambase),
1808 fw->data, fw->size);
1809 #endif
1810
1811 resetintr = get_unaligned_le32(fw->data);
1812 release_firmware(fw);
1813
1814 /* reset last 4 bytes of RAM address. to be used for shared
1815 * area. This identifies when FW is running
1816 */
1817 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1818
1819 if (nvram) {
1820 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1821 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1822 nvram_len;
1823 #if defined(__linux__)
1824 memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1825 #elif defined(__FreeBSD__)
1826 memcpy_toio((void *)((uintptr_t)devinfo->tcm + address), nvram, nvram_len);
1827 #endif
1828 brcmf_fw_nvram_free(nvram);
1829
1830 if (devinfo->fwseed) {
1831 size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
1832 struct brcmf_random_seed_footer footer = {
1833 .length = cpu_to_le32(rand_len),
1834 .magic = cpu_to_le32(BRCMF_RANDOM_SEED_MAGIC),
1835 };
1836
1837 /* Some chips/firmwares expect a buffer of random
1838 * data to be present before NVRAM
1839 */
1840 brcmf_dbg(PCIE, "Download random seed\n");
1841
1842 address -= sizeof(footer);
1843 #if defined(__linux__)
1844 memcpy_toio(devinfo->tcm + address, &footer,
1845 #elif defined(__FreeBSD__)
1846 memcpy_toio((void *)((uintptr_t)devinfo->tcm + address), &footer,
1847 #endif
1848 sizeof(footer));
1849
1850 address -= rand_len;
1851 brcmf_pcie_provide_random_bytes(devinfo, address);
1852 }
1853 } else {
1854 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1855 devinfo->nvram_name);
1856 }
1857
1858 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1859 devinfo->ci->ramsize -
1860 4);
1861 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1862 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1863 if (err)
1864 return err;
1865
1866 brcmf_dbg(PCIE, "Wait for FW init\n");
1867 sharedram_addr = sharedram_addr_written;
1868 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1869 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1870 #if defined(__linux__)
1871 msleep(50);
1872 #elif defined(__FreeBSD__)
1873 linux_msleep(50);
1874 #endif
1875 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1876 devinfo->ci->ramsize -
1877 4);
1878 loop_counter--;
1879 }
1880 if (sharedram_addr == sharedram_addr_written) {
1881 brcmf_err(bus, "FW failed to initialize\n");
1882 return -ENODEV;
1883 }
1884 if (sharedram_addr < devinfo->ci->rambase ||
1885 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) {
1886 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n",
1887 sharedram_addr);
1888 return -ENODEV;
1889 }
1890 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1891
1892 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1893 }
1894
1895
brcmf_pcie_get_resource(struct brcmf_pciedev_info * devinfo)1896 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1897 {
1898 struct pci_dev *pdev = devinfo->pdev;
1899 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1900 int err;
1901 phys_addr_t bar0_addr, bar1_addr;
1902 ulong bar1_size;
1903
1904 err = pci_enable_device(pdev);
1905 if (err) {
1906 brcmf_err(bus, "pci_enable_device failed err=%d\n", err);
1907 return err;
1908 }
1909
1910 pci_set_master(pdev);
1911
1912 /* Bar-0 mapped address */
1913 bar0_addr = pci_resource_start(pdev, 0);
1914 /* Bar-1 mapped address */
1915 bar1_addr = pci_resource_start(pdev, 2);
1916 /* read Bar-1 mapped memory range */
1917 bar1_size = pci_resource_len(pdev, 2);
1918 if ((bar1_size == 0) || (bar1_addr == 0)) {
1919 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1920 bar1_size, (unsigned long long)bar1_addr);
1921 return -EINVAL;
1922 }
1923
1924 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1925 devinfo->tcm = ioremap(bar1_addr, bar1_size);
1926
1927 if (!devinfo->regs || !devinfo->tcm) {
1928 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs,
1929 devinfo->tcm);
1930 return -EINVAL;
1931 }
1932 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1933 devinfo->regs, (unsigned long long)bar0_addr);
1934 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1935 devinfo->tcm, (unsigned long long)bar1_addr,
1936 (unsigned int)bar1_size);
1937
1938 return 0;
1939 }
1940
1941
brcmf_pcie_release_resource(struct brcmf_pciedev_info * devinfo)1942 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1943 {
1944 if (devinfo->tcm)
1945 iounmap(devinfo->tcm);
1946 if (devinfo->regs)
1947 iounmap(devinfo->regs);
1948
1949 pci_disable_device(devinfo->pdev);
1950 }
1951
1952
brcmf_pcie_buscore_prep_addr(const struct pci_dev * pdev,u32 addr)1953 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1954 {
1955 u32 ret_addr;
1956
1957 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1958 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1959 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1960
1961 return ret_addr;
1962 }
1963
1964
brcmf_pcie_buscore_read32(void * ctx,u32 addr)1965 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1966 {
1967 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1968
1969 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1970 return brcmf_pcie_read_reg32(devinfo, addr);
1971 }
1972
1973
brcmf_pcie_buscore_write32(void * ctx,u32 addr,u32 value)1974 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1975 {
1976 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1977
1978 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1979 brcmf_pcie_write_reg32(devinfo, addr, value);
1980 }
1981
1982
brcmf_pcie_buscoreprep(void * ctx)1983 static int brcmf_pcie_buscoreprep(void *ctx)
1984 {
1985 return brcmf_pcie_get_resource(ctx);
1986 }
1987
1988
brcmf_pcie_buscore_reset(void * ctx,struct brcmf_chip * chip)1989 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1990 {
1991 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1992 struct brcmf_core *core;
1993 u32 val, reg;
1994
1995 devinfo->ci = chip;
1996 brcmf_pcie_reset_device(devinfo);
1997
1998 /* reginfo is not ready yet */
1999 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2);
2000 if (core->rev >= 64)
2001 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT;
2002 else
2003 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT;
2004
2005 val = brcmf_pcie_read_reg32(devinfo, reg);
2006 if (val != 0xffffffff)
2007 brcmf_pcie_write_reg32(devinfo, reg, val);
2008
2009 return 0;
2010 }
2011
2012
brcmf_pcie_buscore_activate(void * ctx,struct brcmf_chip * chip,u32 rstvec)2013 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
2014 u32 rstvec)
2015 {
2016 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
2017
2018 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
2019 }
2020
2021
2022 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
2023 .prepare = brcmf_pcie_buscoreprep,
2024 .reset = brcmf_pcie_buscore_reset,
2025 .activate = brcmf_pcie_buscore_activate,
2026 .read32 = brcmf_pcie_buscore_read32,
2027 .write32 = brcmf_pcie_buscore_write32,
2028 };
2029
2030 #define BRCMF_OTP_SYS_VENDOR 0x15
2031 #define BRCMF_OTP_BRCM_CIS 0x80
2032
2033 #define BRCMF_OTP_VENDOR_HDR 0x00000008
2034
2035 static int
brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info * devinfo,u8 * data,size_t size)2036 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo,
2037 u8 *data, size_t size)
2038 {
2039 int idx = 4;
2040 const char *chip_params;
2041 const char *board_params;
2042 const char *p;
2043
2044 /* 4-byte header and two empty strings */
2045 if (size < 6)
2046 return -EINVAL;
2047
2048 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR)
2049 return -EINVAL;
2050
2051 chip_params = &data[idx];
2052
2053 /* Skip first string, including terminator */
2054 idx += strnlen(chip_params, size - idx) + 1;
2055 if (idx >= size)
2056 return -EINVAL;
2057
2058 board_params = &data[idx];
2059
2060 /* Skip to terminator of second string */
2061 idx += strnlen(board_params, size - idx);
2062 if (idx >= size)
2063 return -EINVAL;
2064
2065 /* At this point both strings are guaranteed NUL-terminated */
2066 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n",
2067 chip_params, board_params);
2068
2069 p = skip_spaces(board_params);
2070 while (*p) {
2071 char tag = *p++;
2072 const char *end;
2073 size_t len;
2074
2075 if (*p++ != '=') /* implicit NUL check */
2076 return -EINVAL;
2077
2078 /* *p might be NUL here, if so end == p and len == 0 */
2079 end = strchrnul(p, ' ');
2080 len = end - p;
2081
2082 /* leave 1 byte for NUL in destination string */
2083 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1))
2084 return -EINVAL;
2085
2086 /* Copy len characters plus a NUL terminator */
2087 switch (tag) {
2088 case 'M':
2089 strscpy(devinfo->otp.module, p, len + 1);
2090 break;
2091 case 'V':
2092 strscpy(devinfo->otp.vendor, p, len + 1);
2093 break;
2094 case 'm':
2095 strscpy(devinfo->otp.version, p, len + 1);
2096 break;
2097 }
2098
2099 /* Skip to next arg, if any */
2100 p = skip_spaces(end);
2101 }
2102
2103 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n",
2104 devinfo->otp.module, devinfo->otp.vendor,
2105 devinfo->otp.version);
2106
2107 if (!devinfo->otp.module[0] ||
2108 !devinfo->otp.vendor[0] ||
2109 !devinfo->otp.version[0])
2110 return -EINVAL;
2111
2112 devinfo->otp.valid = true;
2113 return 0;
2114 }
2115
2116 static int
brcmf_pcie_parse_otp(struct brcmf_pciedev_info * devinfo,u8 * otp,size_t size)2117 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size)
2118 {
2119 int p = 0;
2120 int ret = -EINVAL;
2121
2122 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size);
2123
2124 while (p < (size - 1)) {
2125 u8 type = otp[p];
2126 u8 length = otp[p + 1];
2127
2128 if (type == 0)
2129 break;
2130
2131 if ((p + 2 + length) > size)
2132 break;
2133
2134 switch (type) {
2135 case BRCMF_OTP_SYS_VENDOR:
2136 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n",
2137 p, length);
2138 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo,
2139 &otp[p + 2],
2140 length);
2141 break;
2142 case BRCMF_OTP_BRCM_CIS:
2143 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n",
2144 p, length);
2145 break;
2146 default:
2147 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n",
2148 p, length, type);
2149 break;
2150 }
2151
2152 p += 2 + length;
2153 }
2154
2155 return ret;
2156 }
2157
brcmf_pcie_read_otp(struct brcmf_pciedev_info * devinfo)2158 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo)
2159 {
2160 const struct pci_dev *pdev = devinfo->pdev;
2161 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
2162 u32 coreid, base, words, idx, sromctl;
2163 u16 *otp;
2164 struct brcmf_core *core;
2165 int ret;
2166
2167 switch (devinfo->ci->chip) {
2168 case BRCM_CC_4355_CHIP_ID:
2169 coreid = BCMA_CORE_CHIPCOMMON;
2170 base = 0x8c0;
2171 words = 0xb2;
2172 break;
2173 case BRCM_CC_4364_CHIP_ID:
2174 coreid = BCMA_CORE_CHIPCOMMON;
2175 base = 0x8c0;
2176 words = 0x1a0;
2177 break;
2178 case BRCM_CC_4377_CHIP_ID:
2179 case BRCM_CC_4378_CHIP_ID:
2180 coreid = BCMA_CORE_GCI;
2181 base = 0x1120;
2182 words = 0x170;
2183 break;
2184 case BRCM_CC_4387_CHIP_ID:
2185 coreid = BCMA_CORE_GCI;
2186 base = 0x113c;
2187 words = 0x170;
2188 break;
2189 default:
2190 /* OTP not supported on this chip */
2191 return 0;
2192 }
2193
2194 core = brcmf_chip_get_core(devinfo->ci, coreid);
2195 if (!core) {
2196 brcmf_err(bus, "No OTP core\n");
2197 return -ENODEV;
2198 }
2199
2200 if (coreid == BCMA_CORE_CHIPCOMMON) {
2201 /* Chips with OTP accessed via ChipCommon need additional
2202 * handling to access the OTP
2203 */
2204 brcmf_pcie_select_core(devinfo, coreid);
2205 sromctl = READCC32(devinfo, sromcontrol);
2206
2207 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) {
2208 /* Chip lacks OTP, try without it... */
2209 brcmf_err(bus,
2210 "OTP unavailable, using default firmware\n");
2211 return 0;
2212 }
2213
2214 /* Map OTP to shadow area */
2215 WRITECC32(devinfo, sromcontrol,
2216 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL);
2217 }
2218
2219 otp = kcalloc(words, sizeof(u16), GFP_KERNEL);
2220 if (!otp)
2221 return -ENOMEM;
2222
2223 /* Map bus window to SROM/OTP shadow area in core */
2224 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base);
2225
2226 brcmf_dbg(PCIE, "OTP data:\n");
2227 for (idx = 0; idx < words; idx++) {
2228 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx);
2229 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]);
2230 }
2231
2232 if (coreid == BCMA_CORE_CHIPCOMMON) {
2233 brcmf_pcie_select_core(devinfo, coreid);
2234 WRITECC32(devinfo, sromcontrol, sromctl);
2235 }
2236
2237 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words);
2238 kfree(otp);
2239
2240 return ret;
2241 }
2242
2243 #define BRCMF_PCIE_FW_CODE 0
2244 #define BRCMF_PCIE_FW_NVRAM 1
2245 #define BRCMF_PCIE_FW_CLM 2
2246 #define BRCMF_PCIE_FW_TXCAP 3
2247
brcmf_pcie_setup(struct device * dev,int ret,struct brcmf_fw_request * fwreq)2248 static void brcmf_pcie_setup(struct device *dev, int ret,
2249 struct brcmf_fw_request *fwreq)
2250 {
2251 const struct firmware *fw;
2252 void *nvram;
2253 struct brcmf_bus *bus;
2254 struct brcmf_pciedev *pcie_bus_dev;
2255 struct brcmf_pciedev_info *devinfo;
2256 struct brcmf_commonring **flowrings;
2257 u32 i, nvram_len;
2258
2259 bus = dev_get_drvdata(dev);
2260 pcie_bus_dev = bus->bus_priv.pcie;
2261 devinfo = pcie_bus_dev->devinfo;
2262
2263 /* check firmware loading result */
2264 if (ret)
2265 goto fail;
2266
2267 brcmf_pcie_attach(devinfo);
2268
2269 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
2270 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data;
2271 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len;
2272 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary;
2273 devinfo->txcap_fw = fwreq->items[BRCMF_PCIE_FW_TXCAP].binary;
2274 kfree(fwreq);
2275
2276 ret = brcmf_chip_get_raminfo(devinfo->ci);
2277 if (ret) {
2278 brcmf_err(bus, "Failed to get RAM info\n");
2279 release_firmware(fw);
2280 brcmf_fw_nvram_free(nvram);
2281 goto fail;
2282 }
2283
2284 /* Some of the firmwares have the size of the memory of the device
2285 * defined inside the firmware. This is because part of the memory in
2286 * the device is shared and the devision is determined by FW. Parse
2287 * the firmware and adjust the chip memory size now.
2288 */
2289 #if defined(__linux__)
2290 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
2291 #elif defined(__FreeBSD__)
2292 brcmf_pcie_adjust_ramsize(devinfo, fw->data, fw->size);
2293 #endif
2294
2295 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
2296 if (ret)
2297 goto fail;
2298
2299 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2300
2301 ret = brcmf_pcie_init_ringbuffers(devinfo);
2302 if (ret)
2303 goto fail;
2304
2305 ret = brcmf_pcie_init_scratchbuffers(devinfo);
2306 if (ret)
2307 goto fail;
2308
2309 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2310 ret = brcmf_pcie_request_irq(devinfo);
2311 if (ret)
2312 goto fail;
2313
2314 /* hook the commonrings in the bus structure. */
2315 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
2316 bus->msgbuf->commonrings[i] =
2317 &devinfo->shared.commonrings[i]->commonring;
2318
2319 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
2320 GFP_KERNEL);
2321 if (!flowrings)
2322 goto fail;
2323
2324 for (i = 0; i < devinfo->shared.max_flowrings; i++)
2325 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
2326 bus->msgbuf->flowrings = flowrings;
2327
2328 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
2329 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
2330 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
2331
2332 init_waitqueue_head(&devinfo->mbdata_resp_wait);
2333
2334 ret = brcmf_attach(&devinfo->pdev->dev);
2335 if (ret)
2336 goto fail;
2337
2338 brcmf_pcie_bus_console_read(devinfo, false);
2339
2340 brcmf_pcie_fwcon_timer(devinfo, true);
2341
2342 return;
2343
2344 fail:
2345 brcmf_err(bus, "Dongle setup failed\n");
2346 brcmf_pcie_bus_console_read(devinfo, true);
2347 brcmf_fw_crashed(dev);
2348 device_release_driver(dev);
2349 }
2350
2351 static struct brcmf_fw_request *
brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info * devinfo)2352 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
2353 {
2354 struct brcmf_fw_request *fwreq;
2355 struct brcmf_fw_name fwnames[] = {
2356 { ".bin", devinfo->fw_name },
2357 { ".txt", devinfo->nvram_name },
2358 { ".clm_blob", devinfo->clm_name },
2359 { ".txcap_blob", devinfo->txcap_name },
2360 };
2361
2362 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev,
2363 brcmf_pcie_fwnames,
2364 ARRAY_SIZE(brcmf_pcie_fwnames),
2365 fwnames, ARRAY_SIZE(fwnames));
2366 if (!fwreq)
2367 return NULL;
2368
2369 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
2370 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
2371 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL;
2372 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY;
2373 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL;
2374 fwreq->items[BRCMF_PCIE_FW_TXCAP].type = BRCMF_FW_TYPE_BINARY;
2375 fwreq->items[BRCMF_PCIE_FW_TXCAP].flags = BRCMF_FW_REQF_OPTIONAL;
2376 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */
2377 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1;
2378 fwreq->bus_nr = devinfo->pdev->bus->number;
2379
2380 /* Apple platforms with fancy firmware/NVRAM selection */
2381 if (devinfo->settings->board_type &&
2382 devinfo->settings->antenna_sku &&
2383 devinfo->otp.valid) {
2384 const struct brcmf_otp_params *otp = &devinfo->otp;
2385 struct device *dev = &devinfo->pdev->dev;
2386 const char **bt = fwreq->board_types;
2387
2388 brcmf_dbg(PCIE, "Apple board: %s\n",
2389 devinfo->settings->board_type);
2390
2391 /* Example: apple,shikoku-RASP-m-6.11-X3 */
2392 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s",
2393 devinfo->settings->board_type,
2394 otp->module, otp->vendor, otp->version,
2395 devinfo->settings->antenna_sku);
2396 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s",
2397 devinfo->settings->board_type,
2398 otp->module, otp->vendor, otp->version);
2399 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s",
2400 devinfo->settings->board_type,
2401 otp->module, otp->vendor);
2402 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2403 devinfo->settings->board_type,
2404 otp->module);
2405 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2406 devinfo->settings->board_type,
2407 devinfo->settings->antenna_sku);
2408 bt[5] = devinfo->settings->board_type;
2409
2410 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) {
2411 kfree(fwreq);
2412 return NULL;
2413 }
2414 } else {
2415 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type);
2416 fwreq->board_types[0] = devinfo->settings->board_type;
2417 }
2418
2419 return fwreq;
2420 }
2421
2422 #ifdef DEBUG
2423 static void
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info * devinfo,bool active)2424 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2425 {
2426 if (!active) {
2427 if (devinfo->console_active) {
2428 timer_delete_sync(&devinfo->timer);
2429 devinfo->console_active = false;
2430 }
2431 return;
2432 }
2433
2434 /* don't start the timer */
2435 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP ||
2436 !devinfo->console_interval || !BRCMF_FWCON_ON())
2437 return;
2438
2439 if (!devinfo->console_active) {
2440 devinfo->timer.expires = jiffies + devinfo->console_interval;
2441 add_timer(&devinfo->timer);
2442 devinfo->console_active = true;
2443 } else {
2444 /* Reschedule the timer */
2445 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2446 }
2447 }
2448
2449 static void
brcmf_pcie_fwcon(struct timer_list * t)2450 brcmf_pcie_fwcon(struct timer_list *t)
2451 {
2452 struct brcmf_pciedev_info *devinfo = timer_container_of(devinfo, t,
2453 timer);
2454
2455 if (!devinfo->console_active)
2456 return;
2457
2458 brcmf_pcie_bus_console_read(devinfo, false);
2459
2460 /* Reschedule the timer if console interval is not zero */
2461 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2462 }
2463
brcmf_pcie_console_interval_get(void * data,u64 * val)2464 static int brcmf_pcie_console_interval_get(void *data, u64 *val)
2465 {
2466 struct brcmf_pciedev_info *devinfo = data;
2467
2468 *val = devinfo->console_interval;
2469
2470 return 0;
2471 }
2472
brcmf_pcie_console_interval_set(void * data,u64 val)2473 static int brcmf_pcie_console_interval_set(void *data, u64 val)
2474 {
2475 struct brcmf_pciedev_info *devinfo = data;
2476
2477 if (val > MAX_CONSOLE_INTERVAL)
2478 return -EINVAL;
2479
2480 devinfo->console_interval = val;
2481
2482 if (!val && devinfo->console_active)
2483 brcmf_pcie_fwcon_timer(devinfo, false);
2484 else if (val)
2485 brcmf_pcie_fwcon_timer(devinfo, true);
2486
2487 return 0;
2488 }
2489
2490 DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops,
2491 brcmf_pcie_console_interval_get,
2492 brcmf_pcie_console_interval_set,
2493 "%llu\n");
2494
brcmf_pcie_debugfs_create(struct device * dev)2495 static void brcmf_pcie_debugfs_create(struct device *dev)
2496 {
2497 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2498 struct brcmf_pub *drvr = bus_if->drvr;
2499 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
2500 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
2501 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
2502
2503 if (IS_ERR_OR_NULL(dentry))
2504 return;
2505
2506 devinfo->console_interval = BRCMF_CONSOLE;
2507
2508 debugfs_create_file("console_interval", 0644, dentry, devinfo,
2509 &brcmf_pcie_console_interval_fops);
2510 }
2511
2512 #else
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info * devinfo,bool active)2513 void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2514 {
2515 }
2516
brcmf_pcie_debugfs_create(struct device * dev)2517 static void brcmf_pcie_debugfs_create(struct device *dev)
2518 {
2519 }
2520 #endif
2521
2522 struct brcmf_pcie_drvdata {
2523 enum brcmf_fwvendor vendor;
2524 bool fw_seed;
2525 };
2526
2527 enum {
2528 BRCMF_DRVDATA_CYW,
2529 BRCMF_DRVDATA_BCA,
2530 BRCMF_DRVDATA_WCC,
2531 BRCMF_DRVDATA_WCC_SEED,
2532 };
2533
2534 static const struct brcmf_pcie_drvdata drvdata[] = {
2535 [BRCMF_DRVDATA_CYW] = {
2536 .vendor = BRCMF_FWVENDOR_CYW,
2537 .fw_seed = false,
2538 },
2539 [BRCMF_DRVDATA_BCA] = {
2540 .vendor = BRCMF_FWVENDOR_BCA,
2541 .fw_seed = false,
2542 },
2543 [BRCMF_DRVDATA_WCC] = {
2544 .vendor = BRCMF_FWVENDOR_WCC,
2545 .fw_seed = false,
2546 },
2547 [BRCMF_DRVDATA_WCC_SEED] = {
2548 .vendor = BRCMF_FWVENDOR_WCC,
2549 .fw_seed = true,
2550 },
2551 };
2552
2553 /* Forward declaration for pci_match_id() call */
2554 static const struct pci_device_id brcmf_pcie_devid_table[];
2555
2556 static int
brcmf_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * id)2557 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2558 {
2559 int ret;
2560 struct brcmf_fw_request *fwreq;
2561 struct brcmf_pciedev_info *devinfo;
2562 struct brcmf_pciedev *pcie_bus_dev;
2563 struct brcmf_core *core;
2564 struct brcmf_bus *bus;
2565
2566 if (!id) {
2567 id = pci_match_id(brcmf_pcie_devid_table, pdev);
2568 if (!id) {
2569 pci_err(pdev, "Error could not find pci_device_id for %x:%x\n", pdev->vendor, pdev->device);
2570 return -ENODEV;
2571 }
2572 }
2573
2574 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
2575
2576 ret = -ENOMEM;
2577 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
2578 if (devinfo == NULL)
2579 return ret;
2580
2581 devinfo->pdev = pdev;
2582 pcie_bus_dev = NULL;
2583 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device,
2584 &brcmf_pcie_buscore_ops);
2585 if (IS_ERR(devinfo->ci)) {
2586 ret = PTR_ERR(devinfo->ci);
2587 devinfo->ci = NULL;
2588 goto fail;
2589 }
2590
2591 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
2592 if (core->rev >= 64)
2593 devinfo->reginfo = &brcmf_reginfo_64;
2594 else
2595 devinfo->reginfo = &brcmf_reginfo_default;
2596
2597 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
2598 if (pcie_bus_dev == NULL) {
2599 ret = -ENOMEM;
2600 goto fail;
2601 }
2602
2603 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
2604 BRCMF_BUSTYPE_PCIE,
2605 devinfo->ci->chip,
2606 devinfo->ci->chiprev);
2607 if (!devinfo->settings) {
2608 ret = -ENOMEM;
2609 goto fail;
2610 }
2611 ret = PTR_ERR_OR_ZERO(devinfo->settings);
2612 if (ret < 0)
2613 goto fail;
2614
2615 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
2616 if (!bus) {
2617 ret = -ENOMEM;
2618 goto fail;
2619 }
2620 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
2621 if (!bus->msgbuf) {
2622 ret = -ENOMEM;
2623 kfree(bus);
2624 goto fail;
2625 }
2626
2627 /* hook it all together. */
2628 pcie_bus_dev->devinfo = devinfo;
2629 pcie_bus_dev->bus = bus;
2630 bus->dev = &pdev->dev;
2631 bus->bus_priv.pcie = pcie_bus_dev;
2632 bus->ops = &brcmf_pcie_bus_ops;
2633 bus->proto_type = BRCMF_PROTO_MSGBUF;
2634 bus->chip = devinfo->coreid;
2635 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
2636 bus->fwvid = drvdata[id->driver_data].vendor;
2637 devinfo->fwseed = drvdata[id->driver_data].fw_seed;
2638 dev_set_drvdata(&pdev->dev, bus);
2639
2640 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings);
2641 if (ret)
2642 goto fail_bus;
2643
2644 /* otp read operation */
2645 switch (bus->fwvid) {
2646 case BRCMF_FWVENDOR_WCC:
2647 case BRCMF_FWVENDOR_BCA:
2648 ret = brcmf_pcie_read_otp(devinfo);
2649 if (ret) {
2650 brcmf_err(bus, "failed to parse OTP\n");
2651 goto fail_brcmf;
2652 }
2653 break;
2654 case BRCMF_FWVENDOR_CYW:
2655 default:
2656 break;
2657 }
2658
2659 #ifdef DEBUG
2660 /* Set up the fwcon timer */
2661 timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0);
2662 #endif
2663
2664 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
2665 if (!fwreq) {
2666 ret = -ENOMEM;
2667 goto fail_brcmf;
2668 }
2669
2670 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup);
2671 if (ret < 0) {
2672 kfree(fwreq);
2673 goto fail_brcmf;
2674 }
2675 return 0;
2676
2677 fail_brcmf:
2678 brcmf_free(&devinfo->pdev->dev);
2679 fail_bus:
2680 kfree(bus->msgbuf);
2681 kfree(bus);
2682 fail:
2683 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device);
2684 brcmf_pcie_release_resource(devinfo);
2685 if (devinfo->ci)
2686 brcmf_chip_detach(devinfo->ci);
2687 if (devinfo->settings)
2688 brcmf_release_module_param(devinfo->settings);
2689 kfree(pcie_bus_dev);
2690 kfree(devinfo);
2691 return ret;
2692 }
2693
2694
2695 static void
brcmf_pcie_remove(struct pci_dev * pdev)2696 brcmf_pcie_remove(struct pci_dev *pdev)
2697 {
2698 struct brcmf_pciedev_info *devinfo;
2699 struct brcmf_bus *bus;
2700
2701 brcmf_dbg(PCIE, "Enter\n");
2702
2703 bus = dev_get_drvdata(&pdev->dev);
2704 if (bus == NULL)
2705 return;
2706
2707 devinfo = bus->bus_priv.pcie->devinfo;
2708 brcmf_pcie_bus_console_read(devinfo, false);
2709 brcmf_pcie_fwcon_timer(devinfo, false);
2710
2711 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2712 if (devinfo->ci)
2713 brcmf_pcie_intr_disable(devinfo);
2714
2715 brcmf_detach(&pdev->dev);
2716 brcmf_free(&pdev->dev);
2717
2718 kfree(bus->bus_priv.pcie);
2719 kfree(bus->msgbuf->flowrings);
2720 kfree(bus->msgbuf);
2721 kfree(bus);
2722
2723 brcmf_pcie_release_irq(devinfo);
2724 brcmf_pcie_release_scratchbuffers(devinfo);
2725 brcmf_pcie_release_ringbuffers(devinfo);
2726 brcmf_pcie_reset_device(devinfo);
2727 brcmf_pcie_release_resource(devinfo);
2728 release_firmware(devinfo->clm_fw);
2729 release_firmware(devinfo->txcap_fw);
2730
2731 if (devinfo->ci)
2732 brcmf_chip_detach(devinfo->ci);
2733 if (devinfo->settings)
2734 brcmf_release_module_param(devinfo->settings);
2735
2736 kfree(devinfo);
2737 dev_set_drvdata(&pdev->dev, NULL);
2738 }
2739
2740
2741 #ifdef CONFIG_PM
2742
2743
brcmf_pcie_pm_enter_D3(struct device * dev)2744 static int brcmf_pcie_pm_enter_D3(struct device *dev)
2745 {
2746 struct brcmf_pciedev_info *devinfo;
2747 struct brcmf_bus *bus;
2748
2749 brcmf_dbg(PCIE, "Enter\n");
2750
2751 bus = dev_get_drvdata(dev);
2752 devinfo = bus->bus_priv.pcie->devinfo;
2753
2754 brcmf_pcie_fwcon_timer(devinfo, false);
2755 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
2756
2757 devinfo->mbdata_completed = false;
2758 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
2759
2760 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
2761 BRCMF_PCIE_MBDATA_TIMEOUT);
2762 if (!devinfo->mbdata_completed) {
2763 brcmf_err(bus, "Timeout on response for entering D3 substate\n");
2764 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2765 return -EIO;
2766 }
2767
2768 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2769
2770 return 0;
2771 }
2772
2773
brcmf_pcie_pm_leave_D3(struct device * dev)2774 static int brcmf_pcie_pm_leave_D3(struct device *dev)
2775 {
2776 struct brcmf_pciedev_info *devinfo;
2777 struct brcmf_bus *bus;
2778 struct pci_dev *pdev;
2779 int err;
2780
2781 brcmf_dbg(PCIE, "Enter\n");
2782
2783 bus = dev_get_drvdata(dev);
2784 devinfo = bus->bus_priv.pcie->devinfo;
2785 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
2786
2787 /* Check if device is still up and running, if so we are ready */
2788 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) {
2789 brcmf_dbg(PCIE, "Try to wakeup device....\n");
2790 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
2791 goto cleanup;
2792 brcmf_dbg(PCIE, "Hot resume, continue....\n");
2793 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2794 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2795 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2796 brcmf_pcie_intr_enable(devinfo);
2797 brcmf_pcie_hostready(devinfo);
2798 brcmf_pcie_fwcon_timer(devinfo, true);
2799 return 0;
2800 }
2801
2802 cleanup:
2803 brcmf_chip_detach(devinfo->ci);
2804 devinfo->ci = NULL;
2805 pdev = devinfo->pdev;
2806 brcmf_pcie_remove(pdev);
2807
2808 err = brcmf_pcie_probe(pdev, NULL);
2809 if (err)
2810 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err);
2811
2812 return err;
2813 }
2814
2815
2816 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
2817 .suspend = brcmf_pcie_pm_enter_D3,
2818 .resume = brcmf_pcie_pm_leave_D3,
2819 .freeze = brcmf_pcie_pm_enter_D3,
2820 .restore = brcmf_pcie_pm_leave_D3,
2821 };
2822
2823
2824 #endif /* CONFIG_PM */
2825
2826
2827 #define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \
2828 { \
2829 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2830 PCI_ANY_ID, PCI_ANY_ID, \
2831 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2832 BRCMF_DRVDATA_ ## fw_vend \
2833 }
2834 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \
2835 { \
2836 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2837 (subvend), (subdev), \
2838 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2839 BRCMF_DRVDATA_ ## fw_vend \
2840 }
2841
2842 static const struct pci_device_id brcmf_pcie_devid_table[] = {
2843 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC),
2844 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC),
2845 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC),
2846 BRCMF_PCIE_DEVICE(BRCM_PCIE_4355_DEVICE_ID, WCC_SEED),
2847 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC),
2848 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC),
2849 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC),
2850 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC),
2851 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC),
2852 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC),
2853 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC),
2854 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC),
2855 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC),
2856 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC),
2857 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, WCC_SEED),
2858 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA),
2859 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA),
2860 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA),
2861 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA),
2862 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA),
2863 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA),
2864 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
2865 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
2866 BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
2867 BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC_SEED),
2868 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC_SEED),
2869 BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC_SEED),
2870 BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC_SEED),
2871 BRCMF_PCIE_DEVICE(CY_PCIE_54591_DEVICE_ID, CYW),
2872 { /* end: all zeroes */ }
2873 };
2874
2875
2876 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2877
2878
2879 static struct pci_driver brcmf_pciedrvr = {
2880 .name = KBUILD_MODNAME,
2881 .id_table = brcmf_pcie_devid_table,
2882 .probe = brcmf_pcie_probe,
2883 .remove = brcmf_pcie_remove,
2884 #ifdef CONFIG_PM
2885 .driver.pm = &brcmf_pciedrvr_pm,
2886 #endif
2887 .driver.coredump = brcmf_dev_coredump,
2888 };
2889
2890
brcmf_pcie_register(void)2891 int brcmf_pcie_register(void)
2892 {
2893 brcmf_dbg(PCIE, "Enter\n");
2894 return pci_register_driver(&brcmf_pciedrvr);
2895 }
2896
2897
brcmf_pcie_exit(void)2898 void brcmf_pcie_exit(void)
2899 {
2900 brcmf_dbg(PCIE, "Enter\n");
2901 pci_unregister_driver(&brcmf_pciedrvr);
2902 }
2903