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Searched refs:rcc (Results 1 – 25 of 53) sorted by relevance

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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32mp151.dtsi135 clocks = <&rcc IPCC>;
140 rcc: rcc@50000000 { label
141 compatible = "st,stm32mp1-rcc", "syscon";
260 clocks = <&rcc SYSCFG>;
267 clocks = <&rcc TMPSENS>;
277 clocks = <&rcc MDMA>;
278 resets = <&rcc MDMA_R>;
289 clocks = <&rcc SDMMC1_K>;
291 resets = <&rcc SDMMC1_R>;
303 clocks = <&rcc SDMMC2_K>;
[all …]
H A Dstm32mp131.dtsi117 clocks = <&rcc TIM2_K>;
152 clocks = <&rcc TIM3_K>;
188 clocks = <&rcc TIM4_K>;
222 clocks = <&rcc TIM5_K>;
258 clocks = <&rcc TIM6_K>;
278 clocks = <&rcc TIM7_K>;
297 clocks = <&rcc LPTIM1_K>;
340 clocks = <&rcc SPI2_K>;
341 resets = <&rcc SPI2_R>;
365 clocks = <&rcc SPI3_K>;
[all …]
H A Dstm32mp133.dtsi18 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
31 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
44 clocks = <&rcc ADC1>, <&rcc ADC1_K>;
83 clocks = <&rcc ETH2MAC>,
84 <&rcc ETH2TX>,
85 <&rcc ETH2RX>,
86 <&rcc ETH2STP>,
87 <&rcc ETH2CK_K>;
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32f769.dtsi15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
H A Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
80 &rcc {
81 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-ed1-scmi.dts38 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
76 &rcc {
77 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
105 clocks = <&rcc
[all...]
H A Dstm32mp153.dtsi41 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
55 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
H A Dstm32mp135.dtsi15 resets = <&rcc DCMIPP_R>;
16 clocks = <&rcc DCMIPP_K>;
28 clocks = <&rcc LTDC_PX>;
H A Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32mp151c-mecio1r0.dts44 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL3_Q>;
45 assigned-clock-parents = <&rcc PLL3_Q>;
H A Dstm32f469.dtsi11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
13 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
H A Dstm32mp157c-odyssey.dts39 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
40 assigned-clock-parents = <&rcc PLL4_P>;
H A Dstm32mp13xf.dtsi12 clocks = <&rcc CRYP1>;
13 resets = <&rcc CRYP1_R>;
H A Dstm32mp15xc.dtsi12 clocks = <&rcc CRYP1>;
13 resets = <&rcc CRYP1_R>;
/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp251.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
246 clocks = <&rcc CK_KER_SPI2>;
247 resets = <&rcc SPI2_R>;
258 clocks = <&rcc CK_KER_SPI3>;
259 resets = <&rcc SPI3_R>;
268 clocks = <&rcc CK_KER_USART2>;
277 clocks = <&rcc CK_KER_USART3>;
286 clocks = <&rcc CK_KER_UART4>;
295 clocks = <&rcc CK_KER_UART5>;
[all …]
H A Dstm32mp253.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dst,stm32-rcc.txt11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
53 - include/dt-bindings/mfd/stm32f4-rcc.h
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
[all …]
H A Dst,stm32h7-rcc.txt11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;

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