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Searched refs:phy (Results 1 – 25 of 1704) sorted by relevance

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/freebsd/sys/dev/isci/scil/
H A Dscic_sds_phy_registers.h78 #define scu_transport_layer_read(phy, reg) \ argument
80 scic_sds_phy_get_controller(phy), \
81 (phy)->transport_layer_registers->reg \
88 #define scu_transport_layer_write(phy, reg, value) \ argument
90 scic_sds_phy_get_controller(phy), \
91 (phy)->transport_layer_registers->reg, \
102 #define SCU_TLCR_READ(phy) \ argument
103 scu_transport_layer_read(phy, control)
108 #define SCU_TLCR_WRITE(phy, value) \ argument
109 scu_transport_layer_write(phy, control, value)
[all …]
/freebsd/sys/net80211/
H A Dieee80211_phy.c79 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
80 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
81 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
82 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
83 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
92 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
93 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },
94 [2] = { .phy = CCK, 5500, 0x04, B(11), 2 },
95 [3] = { .phy = CCK, 11000, 0x04, B(22), 3 },
96 [4] = { .phy = OFDM, 6000, 0x00, 12, 4 },
[all …]
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_ael1002.c97 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms);
99 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
105 err = mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
108 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
115 static void ael100x_txon(struct cphy *phy) in ael100x_txon() argument
117 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; in ael100x_txon()
120 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); in ael100x_txon()
127 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr) in ael_i2c_rd() argument
132 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, in ael_i2c_rd()
139 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); in ael_i2c_rd()
[all …]
H A Dcxgb_aq100x.c66 #define AQ_WRITE_REGS(phy, regs) do { \ argument
69 (void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \
72 #define AQ_READ_REGS(phy, regs) do { \ argument
75 (void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \
83 aq100x_temperature(struct cphy *phy) in aq100x_temperature() argument
87 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) || in aq100x_temperature()
91 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v)) in aq100x_temperature()
98 aq100x_set_defaults(struct cphy *phy) in aq100x_set_defaults() argument
100 return mdio_write(phy, MDIO_DEV_VEND1, AQ_THERMAL_THR, 0x6c00); in aq100x_set_defaults()
104 aq100x_reset(struct cphy *phy, int wait) in aq100x_reset() argument
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/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi212 phy0: ethernet-phy@0 {
215 phy1: ethernet-phy@1 {
218 phy2: ethernet-phy@2 {
221 phy3: ethernet-phy@3 {
224 phy4: ethernet-phy@4 {
227 phy5: ethernet-phy@5 {
230 phy6: ethernet-phy@6 {
233 phy7: ethernet-phy@7 {
236 phy8: ethernet-phy@8 {
239 phy9: ethernet-phy@9 {
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/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_phy.c82 int phy; in ar40xx_phy_tick() local
91 for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) { in ar40xx_phy_tick()
95 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1)); in ar40xx_phy_tick()
97 mii = device_get_softc(sc->sc_phys.miibus[phy]); in ar40xx_phy_tick()
106 "%s: PHY %d: down -> up\n", __func__, phy); in ar40xx_phy_tick()
107 ar40xx_hw_port_link_up(sc, phy + 1); in ar40xx_phy_tick()
108 ar40xx_hw_atu_flush_port(sc, phy + 1); in ar40xx_phy_tick()
113 "%s: PHY %d: up -> down\n", __func__, phy); in ar40xx_phy_tick()
114 ar40xx_hw_port_link_down(sc, phy + 1); in ar40xx_phy_tick()
115 ar40xx_hw_atu_flush_port(sc, phy + 1); in ar40xx_phy_tick()
[all …]
H A Dar40xx_hw_psgmii.c121 ar40xx_hw_psgmii_single_phy_testing(struct ar40xx_softc *sc, int phy) in ar40xx_hw_psgmii_single_phy_testing() argument
130 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x9000); in ar40xx_hw_psgmii_single_phy_testing()
131 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x4140); in ar40xx_hw_psgmii_single_phy_testing()
136 status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11); in ar40xx_hw_psgmii_single_phy_testing()
151 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0000); in ar40xx_hw_psgmii_single_phy_testing()
152 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0003); in ar40xx_hw_psgmii_single_phy_testing()
155 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8020, 0xa000); in ar40xx_hw_psgmii_single_phy_testing()
163 tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e); in ar40xx_hw_psgmii_single_phy_testing()
164 tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d); in ar40xx_hw_psgmii_single_phy_testing()
165 tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f); in ar40xx_hw_psgmii_single_phy_testing()
[all …]
/freebsd/sys/dev/e1000/
H A De1000_phy.c72 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_ops_generic() local
76 phy->ops.init_params = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
77 phy->ops.acquire = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
78 phy->ops.check_polarity = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
79 phy->ops.check_reset_block = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
80 phy->ops.commit = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
81 phy->ops.force_speed_duplex = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
82 phy->ops.get_cfg_done = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
83 phy->ops.get_cable_length = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
84 phy->ops.get_info = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
[all …]
/freebsd/sys/dev/igc/
H A Digc_phy.c20 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic() local
24 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
25 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
26 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
27 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
28 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
29 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
30 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
31 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
32 phy->ops.read_reg_page = igc_null_read_reg; in igc_init_phy_ops_generic()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls2088a-rdb.dts27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
37 phy-handle = <&mdio1_phy3>;
38 phy-connection-type = "10gbase-r";
42 phy-handle = <&mdio1_phy4>;
43 phy-connection-type = "10gbase-r";
47 phy-handle = <&mdio2_phy1>;
48 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-lx2160a-bluebox3.dts57 phy-handle = <&aqr113c_phy1>;
58 phy-mode = "usxgmii";
63 phy-handle = <&aqr113c_phy2>;
64 phy-mode = "usxgmii";
69 phy-handle = <&aqr113c_phy3>;
70 phy-mode = "usxgmii";
75 phy-handle = <&aqr113c_phy4>;
76 phy-mode = "usxgmii";
81 phy-mode = "rgmii";
91 phy-mode = "rgmii";
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dtestmode.c38 mt7915_tm_set_tx_power(struct mt7915_phy *phy) in mt7915_tm_set_tx_power() argument
40 struct mt7915_dev *dev = phy->dev; in mt7915_tm_set_tx_power()
41 struct mt76_phy *mphy = phy->mt76; in mt7915_tm_set_tx_power()
54 .band_idx = phy->mt76->band_idx, in mt7915_tm_set_tx_power()
59 if (phy->mt76->test.state != MT76_TM_STATE_OFF) in mt7915_tm_set_tx_power()
60 tx_power = phy->mt76->test.tx_power; in mt7915_tm_set_tx_power()
74 mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val) in mt7915_tm_set_freq_offset() argument
76 struct mt7915_dev *dev = phy->dev; in mt7915_tm_set_freq_offset()
80 .param.freq.band = phy->mt76->band_idx, in mt7915_tm_set_freq_offset()
106 mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en) in mt7915_tm_set_trx() argument
[all …]
H A Ddebugfs.c52 struct mt7915_phy *phy = file->private_data; in mt7915_sys_recovery_set() local
53 struct mt7915_dev *dev = phy->dev; in mt7915_sys_recovery_set()
54 bool band = phy->mt76->band_idx; in mt7915_sys_recovery_set()
128 struct mt7915_phy *phy = file->private_data; in mt7915_sys_recovery_get() local
129 struct mt7915_dev *dev = phy->dev; in mt7915_sys_recovery_get()
252 struct mt7915_phy *phy = file->private; in mt7915_muru_stats_show() local
253 struct mt7915_dev *dev = phy->dev; in mt7915_muru_stats_show()
277 ret = mt7915_mcu_muru_debug_get(phy); in mt7915_muru_stats_show()
289 phy->mib.dl_cck_cnt, in mt7915_muru_stats_show()
290 phy->mib.dl_ofdm_cnt, in mt7915_muru_stats_show()
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmac80211.c206 static int mt76_led_init(struct mt76_phy *phy) in mt76_led_init() argument
208 struct mt76_dev *dev = phy->dev; in mt76_led_init()
209 struct ieee80211_hw *hw = phy->hw; in mt76_led_init()
211 if (!phy->leds.cdev.brightness_set && !phy->leds.cdev.blink_set) in mt76_led_init()
214 snprintf(phy->leds.name, sizeof(phy->leds.name), "mt76-%s", in mt76_led_init()
217 phy->leds.cdev.name = phy->leds.name; in mt76_led_init()
218 phy->leds.cdev.default_trigger = in mt76_led_init()
225 if (phy == &dev->phy) { in mt76_led_init()
233 phy->leds.pin = led_pin; in mt76_led_init()
234 phy->leds.al = of_property_read_bool(np, in mt76_led_init()
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/freebsd/sys/dev/bxe/
H A Dbxe_elink.c757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
2250 params->phy[phy_index].mdio_ctrl); in elink_set_mdio_emac_per_phy()
2543 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { in elink_xmac_enable()
2574 (params->phy[ELINK_INT_PHY].supported & in elink_xmac_enable()
3413 struct elink_phy *phy, in elink_cl22_write() argument
3420 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in elink_cl22_write()
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in elink_cl22_write()
3425 tmp = ((phy->addr << 21) | (reg << 16) | val | in elink_cl22_write()
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl22_write()
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmain.c17 struct mt7615_phy *phy; in mt7615_dev_running() local
22 phy = mt7615_ext_phy(dev); in mt7615_dev_running()
24 return phy && test_bit(MT76_STATE_RUNNING, &phy->mt76->state); in mt7615_dev_running()
30 struct mt7615_phy *phy = mt7615_hw_phy(hw); in mt7615_start() local
54 if (phy != &dev->phy) { in mt7615_start()
67 ret = mt76_connac_mcu_set_channel_domain(phy->mt76); in mt7615_start()
71 ret = mt76_connac_mcu_set_rate_txpower(phy->mt76); in mt7615_start()
76 ret = mt7615_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH)); in mt7615_start()
80 set_bit(MT76_STATE_RUNNING, &phy->mt76->state); in mt7615_start()
83 ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work, timeout); in mt7615_start()
[all …]
H A Dtestmode.c48 mt7615_tm_set_tx_power(struct mt7615_phy *phy) in mt7615_tm_set_tx_power() argument
50 struct mt7615_dev *dev = phy->dev; in mt7615_tm_set_tx_power()
51 struct mt76_phy *mphy = phy->mt76; in mt7615_tm_set_tx_power()
66 .dbdc_idx = phy != &dev->phy, in mt7615_tm_set_tx_power()
98 mt7615_tm_reg_backup_restore(struct mt7615_phy *phy) in mt7615_tm_reg_backup_restore() argument
100 struct mt7615_dev *dev = phy->dev; in mt7615_tm_reg_backup_restore()
101 u32 *b = phy->test.reg_backup; in mt7615_tm_reg_backup_restore()
106 if (phy->mt76->test.state == MT76_TM_STATE_OFF) { in mt7615_tm_reg_backup_restore()
124 phy->test.reg_backup = b; in mt7615_tm_reg_backup_restore()
133 mt7615_tm_init(struct mt7615_phy *phy) in mt7615_tm_init() argument
[all …]
/freebsd/sys/dev/etherswitch/arswitch/
H A Darswitch_reg.c65 arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, in arswitch_split_setpage() argument
72 *phy = (addr >> 6) & 0x7; in arswitch_split_setpage()
90 uint16_t phy, reg; in arswitch_readreg16() local
92 arswitch_split_setpage(dev, addr, &phy, &reg); in arswitch_readreg16()
93 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); in arswitch_readreg16()
102 uint16_t phy, reg; in arswitch_writereg16() local
104 arswitch_split_setpage(dev, addr, &phy, &reg); in arswitch_writereg16()
105 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); in arswitch_writereg16()
109 arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, in arswitch_writedbg() argument
112 (void) MDIO_WRITEREG(device_get_parent(dev), phy, in arswitch_writedbg()
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_phy.c112 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
189 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_combined_generic_int()
249 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_generic() local
254 phy->ops.identify = ixgbe_identify_phy_generic; in ixgbe_init_phy_ops_generic()
255 phy->ops.reset = ixgbe_reset_phy_generic; in ixgbe_init_phy_ops_generic()
256 phy->ops.read_reg = ixgbe_read_phy_reg_generic; in ixgbe_init_phy_ops_generic()
257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
260 phy->ops.setup_link = ixgbe_setup_phy_link_generic; in ixgbe_init_phy_ops_generic()
[all …]
/freebsd/tools/tools/net80211/wlantxtime/
H A Dwlantxtime.c51 uint8_t phy; /* CCK/OFDM/TURBO */ member
102 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
103 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
104 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
105 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
106 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
115 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
116 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },
117 [2] = { .phy = CCK, 5500, 0x04, B(11), 2 },
118 [3] = { .phy = CCK, 11000, 0x04, B(22), 3 },
[all …]
/freebsd/sys/dev/bwi/
H A Dbwiphy.c156 struct bwi_phy *phy = &mac->mac_phy; in bwi_phy_attach() local
180 phy->phy_init = bwi_phy_init_11a; in bwi_phy_attach()
181 phy->phy_mode = IEEE80211_MODE_11A; in bwi_phy_attach()
182 phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11A; in bwi_phy_attach()
183 phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11A; in bwi_phy_attach()
184 phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11A; in bwi_phy_attach()
189 phy->phy_init = bwi_sup_bphy[i].init; in bwi_phy_attach()
198 phy->phy_mode = IEEE80211_MODE_11B; in bwi_phy_attach()
206 phy->phy_init = bwi_phy_init_11g; in bwi_phy_attach()
207 phy->phy_mode = IEEE80211_MODE_11G; in bwi_phy_attach()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dsamsung-phy.txt6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
35 - "samsung,exynos5250-dp-video-phy"
36 - "samsung,exynos5420-dp-video-phy"
39 - #phy-cells : from the generic PHY bindings, must be 0;
46 - "samsung,exynos3250-usb2-phy"
[all …]
H A Dbrcm-sata-phy.txt5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
16 - reg-names: should be "phy" and "phy-ctrl"
17 The "phy-ctrl" registers are only required for
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt4240qds.dts151 phyrgmii1: ethernet-phy@1 {
155 phyrgmii2: ethernet-phy@2 {
166 phy1: ethernet-phy@0 {
170 phy2: ethernet-phy@1 {
174 phy3: ethernet-phy@2 {
178 phy4: ethernet-phy@3 {
182 sgmiiphy11: ethernet-phy@1c {
186 sgmiiphy12: ethernet-phy@1d {
190 sgmiiphy13: ethernet-phy@1e {
194 sgmiiphy14: ethernet-phy
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-sata.dtsi51 phy-names = "sata-phy";
56 compatible = "brcm,iproc-sr-sata-phy";
58 reg-names = "phy";
63 sata0_phy0: sata-phy@0 {
65 #phy-cells = <0>;
81 phy-names = "sata-phy";
86 compatible = "brcm,iproc-sr-sata-phy";
88 reg-names = "phy";
93 sata1_phy0: sata-phy@0 {
95 #phy-cells = <0>;
[all …]

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