Lines Matching refs:phy
121 ar40xx_hw_psgmii_single_phy_testing(struct ar40xx_softc *sc, int phy) in ar40xx_hw_psgmii_single_phy_testing() argument
130 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x9000); in ar40xx_hw_psgmii_single_phy_testing()
131 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x4140); in ar40xx_hw_psgmii_single_phy_testing()
136 status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11); in ar40xx_hw_psgmii_single_phy_testing()
151 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0000); in ar40xx_hw_psgmii_single_phy_testing()
152 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0003); in ar40xx_hw_psgmii_single_phy_testing()
155 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8020, 0xa000); in ar40xx_hw_psgmii_single_phy_testing()
163 tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e); in ar40xx_hw_psgmii_single_phy_testing()
164 tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d); in ar40xx_hw_psgmii_single_phy_testing()
165 tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f); in ar40xx_hw_psgmii_single_phy_testing()
166 rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b); in ar40xx_hw_psgmii_single_phy_testing()
167 rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a); in ar40xx_hw_psgmii_single_phy_testing()
168 rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c); in ar40xx_hw_psgmii_single_phy_testing()
174 sc->sc_psgmii.phy_t_status &= ~(1U << phy); in ar40xx_hw_psgmii_single_phy_testing()
180 "PHY %d single test PSGMII issue happen!\n", phy); in ar40xx_hw_psgmii_single_phy_testing()
181 sc->sc_psgmii.phy_t_status |= BIT(phy); in ar40xx_hw_psgmii_single_phy_testing()
184 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x1840); in ar40xx_hw_psgmii_single_phy_testing()
191 int phy, j; in ar40xx_hw_psgmii_all_phy_testing() local
197 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { in ar40xx_hw_psgmii_all_phy_testing()
200 status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11); in ar40xx_hw_psgmii_all_phy_testing()
205 if (phy >= (AR40XX_NUM_PORTS - 1)) in ar40xx_hw_psgmii_all_phy_testing()
223 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { in ar40xx_hw_psgmii_all_phy_testing()
231 tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e); in ar40xx_hw_psgmii_all_phy_testing()
232 tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d); in ar40xx_hw_psgmii_all_phy_testing()
233 tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f); in ar40xx_hw_psgmii_all_phy_testing()
234 rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b); in ar40xx_hw_psgmii_all_phy_testing()
235 rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a); in ar40xx_hw_psgmii_all_phy_testing()
236 rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c); in ar40xx_hw_psgmii_all_phy_testing()
242 sc->sc_psgmii.phy_t_status &= ~(1U << (phy + 8)); in ar40xx_hw_psgmii_all_phy_testing()
247 phy, tx_all_ok, rx_all_ok, tx_error, rx_error); in ar40xx_hw_psgmii_all_phy_testing()
248 sc->sc_psgmii.phy_t_status |= (1U << (phy + 8)); in ar40xx_hw_psgmii_all_phy_testing()
322 uint32_t i, phy, reg; in ar40xx_hw_psgmii_self_test() local
330 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { in ar40xx_hw_psgmii_self_test()
332 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x801f); in ar40xx_hw_psgmii_self_test()
347 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { in ar40xx_hw_psgmii_self_test()
351 AR40XX_REG_PORT_LOOKUP(phy + 1)); in ar40xx_hw_psgmii_self_test()
354 AR40XX_REG_PORT_LOOKUP(phy + 1), reg); in ar40xx_hw_psgmii_self_test()
358 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) in ar40xx_hw_psgmii_self_test()
359 ar40xx_hw_psgmii_single_phy_testing(sc, phy); in ar40xx_hw_psgmii_self_test()
390 int phy; in ar40xx_hw_psgmii_self_test_clean() local
398 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { in ar40xx_hw_psgmii_self_test_clean()
400 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(phy + 1)); in ar40xx_hw_psgmii_self_test_clean()
402 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(phy + 1), reg); in ar40xx_hw_psgmii_self_test_clean()
406 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x001f); in ar40xx_hw_psgmii_self_test_clean()