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Searched refs:lmul (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td595 // The set of legal NF for LMUL = lmul.
600 class NFList<int lmul> {
601 list<int> L = !cond(!eq(lmul, 8): [],
602 !eq(lmul, 4): [2],
603 !eq(lmul, 2): [2, 3, 4],
608 class SubRegSet<int nf, int lmul> {
614 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)],
624 // (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul)
633 class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> {
638 !eq(lmul, 1): !listconcat(!range(8, 32), !range(1, 8)),
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H A DRISCVVectorPeephole.cpp306 #define CASE_WHOLE_REGISTER_LMUL_SEW(lmul, sew) \ in convertToWholeRegister() argument
307 case RISCV::PseudoVLE##sew##_V_M##lmul: \ in convertToWholeRegister()
308 NewOpc = RISCV::VL##lmul##RE##sew##_V; \ in convertToWholeRegister()
310 case RISCV::PseudoVSE##sew##_V_M##lmul: \ in convertToWholeRegister()
311 NewOpc = RISCV::VS##lmul##R_V; \ in convertToWholeRegister()
313 #define CASE_WHOLE_REGISTER_LMUL(lmul) \ in convertToWholeRegister() argument
314 CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 8) \ in convertToWholeRegister()
315 CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 16) \ in convertToWholeRegister()
316 CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 32) \ in convertToWholeRegister()
317 CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 64) in convertToWholeRegister()
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H A DRISCVInstrInfoVPseudos.td169 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
171 bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
247 defvar lmul = !shl(1, m.value);
248 list<int> L = NFList<lmul>.L;
1856 foreach lmul = MxSet<eew>.m in {
1857 defvar LInfo = lmul.MX;
1858 defvar vreg = lmul.vrclass;
1859 let VLMul = lmul.value, SEW=eew in {
1874 foreach lmul = MxSet<eew>.m in {
1875 defvar LInfo = lmul.MX;
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H A DRISCVInstrInfoXAndes.td533 foreach lmul = MxSet<8>.m in {
534 defvar LInfo = lmul.MX;
535 defvar vreg = lmul.vrclass;
536 let VLMul = lmul.value in {
H A DRISCVInstrInfoV.td205 class VLESched<string lmul, bit forceMasked = 0> : SchedCommon<
206 [!cast<SchedWrite>("WriteVLDE_" # lmul)],
207 [ReadVLDX], mx=lmul, forceMasked=forceMasked
211 class VSESched<string lmul, bit forceMasked = 0> : SchedCommon<
212 [!cast<SchedWrite>("WriteVSTE_" # lmul)],
213 [!cast<SchedRead>("ReadVSTEV_" # lmul), ReadVSTX], mx=lmul,
253 class VLFSched<string lmul, bit forceMasked = 0> : SchedCommon<
254 [!cast<SchedWrite>("WriteVLDFF_" # lmul)],
255 [ReadVLDX], mx=lmul, forceMasked=forceMasked
H A DRISCVSchedSiFiveP800.td468 // Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.
H A DRISCVSchedSiFiveP400.td508 // Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.
H A DRISCVSchedSiFiveP600.td704 // Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.
H A DRISCVInstrInfoVVLPatterns.td2916 // emul = lmul * 16 / sew
/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm692 my $lmul = read_lmul shift;
695 my $vtypei = ($mask_policy << 7) | ($tail_policy << 6) | ($sew << 3) | $lmul;
706 my $lmul = read_lmul shift;
709 my $vtypei = ($mask_policy << 7) | ($tail_policy << 6) | ($sew << 3) | $lmul;
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector_common.td91 // (eew/sew) * lmul). For example, vector type is __rvv_float16m4
94 // builtins if its equivalent type has illegal lmul.
97 // builtin if its equivalent type has illegal lmul or the SEW does not changed.
101 // define a new builtin if its equivalent type has illegal lmul.
106 // type has illegal lmul.
110 // define a new builtin if its equivalent type has illegal lmul.
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td562 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",