Lines Matching refs:lmul
371 // The set of legal NF for LMUL = lmul.
376 class NFList<int lmul> {
377 list<int> L = !cond(!eq(lmul, 8): [],
378 !eq(lmul, 4): [2],
379 !eq(lmul, 2): [2, 3, 4],
384 class SubRegSet<int nf, int lmul> {
390 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)],
400 // (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul)
409 class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> {
414 !eq(lmul, 1): !listconcat(!range(8, 32), !range(1, 8)),
415 !eq(lmul, 2): !listconcat(!range(4, 16), !range(1, 4)),
416 !eq(lmul, 4): !listconcat(!range(2, 8), !range(1, 2)))),
419 !if(!le(!mul(!add(i, tuple_index), lmul),
420 !sub(!add(32, !mul(tuple_index, lmul)), !mul(nf, lmul))),
421 [!mul(!add(i, tuple_index), lmul)], [])));
430 class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
436 !foreach(i, IndexSet<start, nf, lmul, isV0>.R,
437 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2",
438 !eq(lmul, 4): "M4",
441 !size(IndexSet<start, nf, lmul, isV0>.R)))],
442 VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L));
534 // allocation of higher lmul register groups while still putting v0 last in the