| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.h | 47 Register isStoreToStackSlot(const MachineInstr &MI,
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| H A D | XtensaInstrInfo.cpp | 63 Register XtensaInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function in XtensaInstrInfo
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| H A D | XtensaFrameLowering.cpp | 87 Register Reg = TII.isStoreToStackSlot(*MBBI, StoreFI); in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.h | 49 Register isStoreToStackSlot(const MachineInstr &MI,
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| H A D | XCoreInstrInfo.cpp | 82 Register XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function in XCoreInstrInfo
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.h | 64 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.h | 40 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.h | 48 Register isStoreToStackSlot(const MachineInstr &MI,
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| H A D | ARCInstrInfo.cpp | 87 Register ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function in ARCInstrInfo
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.h | 89 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.h | 42 Register isStoreToStackSlot(const MachineInstr &MI,
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| H A D | Mips16InstrInfo.h | 48 Register isStoreToStackSlot(const MachineInstr &MI,
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| H A D | Mips16InstrInfo.cpp | 64 Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function in Mips16InstrInfo
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.h | 92 Register isStoreToStackSlot(const MachineInstr &MI,
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| H A D | AVRInstrInfo.cpp | 113 Register AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function in llvm::AVRInstrInfo
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 74 Register isStoreToStackSlot(const MachineInstr &MI,
76 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 47 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 286 Register isStoreToStackSlot(const MachineInstr &MI,
288 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 312 virtual Register isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function
321 virtual Register isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot() function
325 return isStoreToStackSlot(MI, FrameIndex); in isStoreToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 366 if (SnipLI.reg() == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) in isSnippet()
539 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { in eliminateRedundantSpills()
823 InstrReg = TII.isStoreToStackSlot(*MI, FI); in coalesceStackAccess()
999 if (TII.isStoreToStackSlot(*MI, FI) && in foldMemoryOperand()
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| H A D | StackSlotColoring.cpp | 487 if (!(StoreReg = TII->isStoreToStackSlot(*NextMI, SecondSS, StoreSize))) in RemoveDeadStores()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 233 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 65 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 201 Register isStoreToStackSlot(const MachineInstr &MI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 424 Register isStoreToStackSlot(const MachineInstr &MI,
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