Home
last modified time | relevance | path

Searched refs:is64BitVector (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp349 bool is64BitVector);
1945 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1947 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2132 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2133 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
2162 if (!is64BitVector) in SelectVLD()
2178 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
2179 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
2247 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2277 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
[all …]
H A DARMISelLowering.cpp6585 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6591 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7441 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
7477 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
7515 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
7548 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
8425 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9677 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
9678 Op1.getValueType().is64BitVector() && in LowerMUL()
12651 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h198 bool is64BitVector() const { in is64BitVector() function
199 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp150 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64ISelLowering.cpp1398 if (VT.is128BitVector() || VT.is64BitVector()) { in AArch64TargetLowering()
2032 bool PreferNEON = VT.is64BitVector() || VT.is128BitVector(); in addTypeForFixedLengthSVE()
5287 assert((VT.is128BitVector() || VT.is64BitVector()) && VT.isInteger() && in LowerMUL()
5293 if (VT.is64BitVector()) { in LowerMUL()
5334 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
5335 Op1.getValueType().is64BitVector() && in LowerMUL()
7118 if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector())) in useSVEForFixedLengthVectorVT()
7360 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
10097 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP_PARITY()
10123 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP_PARITY()
[all …]
H A DAArch64FastISel.cpp2948 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2992 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
H A DAArch64ISelDAGToDAG.cpp170 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
1639 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h142 bool is64BitVector() const { in is64BitVector() function
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24719 assert(StoreVT.is64BitVector() && "Unexpected VT"); in LowerStore()
48575 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
48580 N1.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()