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Searched refs:is64BitVector (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp340 bool is64BitVector);
1936 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1938 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2123 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2124 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
2153 if (!is64BitVector) in SelectVLD()
2169 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
2170 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
2238 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2268 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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H A DARMISelLowering.cpp6651 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6657 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7491 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
7527 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
7565 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
7598 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
8477 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9729 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
9730 Op1.getValueType().is64BitVector() && in LowerMUL()
12718 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h202 bool is64BitVector() const { in is64BitVector() function
203 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp149 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64ISelLowering.cpp1473 if (VT.is128BitVector() || VT.is64BitVector()) { in AArch64TargetLowering()
2238 bool PreferNEON = VT.is64BitVector() || VT.is128BitVector(); in addTypeForFixedLengthSVE()
5438 assert((VT.is128BitVector() || VT.is64BitVector()) && VT.isInteger() && in LowerMUL()
5444 if (VT.is64BitVector()) { in LowerMUL()
5485 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
5486 Op1.getValueType().is64BitVector() && in LowerMUL()
7596 if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector())) in useSVEForFixedLengthVectorVT()
7839 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
10786 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP_PARITY()
10812 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP_PARITY()
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H A DAArch64ISelDAGToDAG.cpp175 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
1651 (VT.is64BitVector() && Subtarget->isLittleEndian())) { in tryIndexedLoad()
1655 } else if (VT.is64BitVector()) { in tryIndexedLoad()
4729 if (SVT.isScalableVector() && VT.is64BitVector()) { in trySelectXAR()
4773 if (VT.is64BitVector() && SVT.isScalableVector()) { in trySelectXAR()
H A DAArch64FastISel.cpp2946 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2990 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h152 bool is64BitVector() const { in is64BitVector() function
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp456 else if (VT.is64BitVector()) in tryEXTRACT_VECTOR_ELEMENT()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp25570 assert(StoreVT.is64BitVector() && "Unexpected VT"); in LowerStore()
50330 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
50335 N1.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()