Lines Matching refs:is64BitVector
349 bool is64BitVector);
1945 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1947 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2132 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2133 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
2162 if (!is64BitVector) in SelectVLD()
2178 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
2179 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
2247 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2277 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
2278 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVST()
2312 if (is64BitVector || NumVecs <= 2) { in SelectVST()
2316 } else if (is64BitVector) { in SelectVST()
2338 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVST()
2432 bool is64BitVector = VT.is64BitVector(); in SelectVLDSTLane() local
2470 if (!is64BitVector) in SelectVLDSTLane()
2496 if (is64BitVector) in SelectVLDSTLane()
2505 if (is64BitVector) in SelectVLDSTLane()
2516 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLDSTLane()
2530 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()
2969 bool is64BitVector = VT.is64BitVector(); in SelectVLDDup() local
3007 if (!is64BitVector) in SelectVLDDup()
3023 unsigned Opc = is64BitVector ? DOpcodes[OpcodeIndex] in SelectVLDDup()
3039 if (is64BitVector || NumVecs == 1) { in SelectVLDDup()
3067 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDDup()
3618 assert((VT.is64BitVector() || VT.is128BitVector()) && in getVectorShuffleOpcode()
3624 return VT.is64BitVector() ? Opc64[0] : Opc128[0]; in getVectorShuffleOpcode()
3626 return VT.is64BitVector() ? Opc64[1] : Opc128[1]; in getVectorShuffleOpcode()
3628 return VT.is64BitVector() ? Opc64[2] : Opc128[2]; in getVectorShuffleOpcode()