| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 207 bool is128BitVector() const { in is128BitVector() function
208 return isSimple() ? V.is128BitVector() : isExtended128BitVector(); in is128BitVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelDAGToDAG.cpp | 102 if (VT.is128BitVector() || VT.is256BitVector()) { in INITIALIZE_PASS()
118 bool Is128Vec = BVN->getValueType(0).is128BitVector(); in INITIALIZE_PASS()
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| H A D | LoongArchISelLowering.cpp | 880 EVT NewVT = ResTy.is128BitVector() ? MVT::v2i64 : MVT::v4i64; in lowerBITREVERSE()
2315 if (VT.is128BitVector()) in lowerVECTOR_SHUFFLE()
2417 assert((VT.is128BitVector() || VT.is256BitVector()) && in lowerBUILD_VECTORAsBroadCastLoad()
2461 bool Is128Vec = ResTy.is128BitVector(); in lowerBUILD_VECTOR()
4351 if ((128 % InBits) == 0 && WidenVT.is128BitVector()) { in ReplaceNodeResults()
6825 else if (ValVT.is128BitVector()) in CC_LoongArch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.h | 162 if (LocVT == MVT::f128 || LocVT.is128BitVector()) { in CC_XPLINK64_Shadow_Reg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 46 else if (LocVT.is128BitVector() || (LocVT == MVT::f128)) { in CC_PPC64_ELF_Shadow_GPR_Regs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 151 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
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| H A D | AArch64ISelLowering.cpp | 1473 if (VT.is128BitVector() || VT.is64BitVector()) { in AArch64TargetLowering()
2238 bool PreferNEON = VT.is64BitVector() || VT.is128BitVector(); in addTypeForFixedLengthSVE()
5205 assert(VT.is128BitVector() && "Unexpected vector MULL size"); in skipExtensionForVectorMULL()
5438 assert((VT.is128BitVector() || VT.is64BitVector()) && VT.isInteger() && in LowerMUL()
5738 if (Op2VT.is128BitVector()) { in LowerVectorMatch()
7596 if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector())) in useSVEForFixedLengthVectorVT()
7841 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
13013 assert((SrcVT.is64BitVector() || SrcVT.is128BitVector()) && in ReconstructShuffle()
13821 if (!Extract.getOperand(0).getValueType().is128BitVector()) in constructDup()
13842 V.getOperand(0).getValueType().is128BitVector()) { in constructDup()
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| H A D | AArch64TargetTransformInfo.cpp | 4100 bool Is128bit = LT.second.is128BitVector(); in getArithmeticInstrCost()
4534 LT.second.is128BitVector() && Alignment < Align(16)) { in getMemoryOpCost()
5593 if (LT.second.is128BitVector() && in getShuffleCost()
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| H A D | AArch64FastISel.cpp | 2947 VT.is128BitVector()) in fastLowerArguments()
2993 } else if (VT.is128BitVector()) { in fastLowerArguments()
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| H A D | AArch64ISelDAGToDAG.cpp | 175 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
1653 } else if (VT.is128BitVector() && Subtarget->isLittleEndian()) { in tryIndexedLoad()
1674 } else if (VT.is128BitVector()) { in tryIndexedLoad()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/ |
| H A D | MachineValueType.h | 157 bool is128BitVector() const { in is128BitVector() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 832 assert(Node->getValueType(0).is128BitVector()); in trySelect()
1051 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector()) in trySelect()
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| H A D | MipsSEISelLowering.cpp | 643 if (!Ty.is128BitVector()) in performORCombine()
1040 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { in performXORCombine()
2455 if (!VecTy.is128BitVector()) in lowerEXTRACT_VECTOR_ELT()
2507 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) in lowerBUILD_VECTOR()
3044 if (!ResTy.is128BitVector()) in lowerVECTOR_SHUFFLE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4057 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || in getZeroVector()
4066 if (!Subtarget.hasSSE2() && VT.is128BitVector()) { in getZeroVector()
4187 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!"); in insert128BitVector()
4738 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && in getOnesVector()
7031 if (!VT.is128BitVector()) in LowerBuildVectorv4x32()
7116 assert(VT.is128BitVector() && "Unknown type for VShift"); in getVShift()
7435 ((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()))) { in EltsFromConsecutiveLoads()
7459 (VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector())) { in EltsFromConsecutiveLoads()
7655 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && in lowerBuildVectorAsBroadcast()
9375 assert((VT.is128BitVector() || VT.is256BitVector() || in LowerBUILD_VECTOR()
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| H A D | X86ISelDAGToDAG.cpp | 652 if (OpVT.is256BitVector() || OpVT.is128BitVector()) in INITIALIZE_PASS()
1103 !(VT.is128BitVector() || VT.is256BitVector())) in PreprocessISelDAG()
4663 if (NVT.is128BitVector()) in matchVPTERNLOG()
4673 if (NVT.is128BitVector()) in matchVPTERNLOG()
4693 if (NVT.is128BitVector()) in matchVPTERNLOG()
5030 unsigned Scale = CmpVT.is128BitVector() ? 4 : 2; in tryVPTESTM()
5031 unsigned SubReg = CmpVT.is128BitVector() ? X86::sub_xmm : X86::sub_ymm; in tryVPTESTM()
5457 if (NVT.is512BitVector() || NVT.is256BitVector() || NVT.is128BitVector() || in Select()
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| H A D | X86ISelLoweringCall.cpp | 1783 else if (RegVT.is128BitVector()) in LowerFormalArguments()
2223 else if (RegVT.is128BitVector()) { in LowerCall()
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| H A D | X86TargetTransformInfo.cpp | 3337 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || in getCmpSelInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2713 assert(VecType.is128BitVector() && "Unexpected shuffle vector type"); in LowerVECTOR_SHUFFLE()
2903 if (!SrcType.is128BitVector() || in performVECTOR_SHUFFLECombine()
3169 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
3203 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6382 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; in getZeroVector()
7061 bool is128Bits = VectorVT.is128BitVector(); in isVMOVModifiedImm()
8183 if (ST->hasNEON() && VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) { in LowerBUILD_VECTOR()
8477 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9285 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && in LowerCONCAT_VECTORS()
9567 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in AddRequiredExtensionForVMULL()
9682 assert(VT.is128BitVector() && VT.isInteger() && in LowerMUL()
10449 if (VT.is128BitVector()) { in LowerVecReduceMinMax()
12758 !N0.getValueType().is128BitVector()) in AddCombineVUZPToVPADDL()
14306 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
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| H A D | ARMISelDAGToDAG.cpp | 3613 assert((VT.is64BitVector() || VT.is128BitVector()) && in getVectorShuffleOpcode()
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