| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 203 bool is128BitVector() const { in is128BitVector() function
204 return isSimple() ? V.is128BitVector() : isExtended128BitVector(); in is128BitVector()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelDAGToDAG.cpp | 85 if (VT.is128BitVector() || VT.is256BitVector()) { in INITIALIZE_PASS()
101 bool Is128Vec = BVN->getValueType(0).is128BitVector(); in INITIALIZE_PASS()
|
| H A D | LoongArchISelLowering.cpp | 1346 if (VT.is128BitVector()) in lowerVECTOR_SHUFFLE()
1380 bool Is128Vec = ResTy.is128BitVector(); in lowerBUILD_VECTOR()
4823 else if (ValVT.is128BitVector()) in CC_LoongArch()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.h | 151 if (LocVT == MVT::f128 || LocVT.is128BitVector()) { in CC_XPLINK64_Shadow_Reg()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 47 else if (LocVT.is128BitVector() || (LocVT == MVT::f128)) { in CC_PPC64_ELF_Shadow_GPR_Regs()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 152 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
|
| H A D | AArch64ISelLowering.cpp | 1398 if (VT.is128BitVector() || VT.is64BitVector()) { in AArch64TargetLowering()
2032 bool PreferNEON = VT.is64BitVector() || VT.is128BitVector(); in addTypeForFixedLengthSVE()
4973 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in addRequiredExtensionForVectorMULL()
5027 assert(VT.is128BitVector() && "Unexpected vector MULL size"); in skipExtensionForVectorMULL()
5287 assert((VT.is128BitVector() || VT.is64BitVector()) && VT.isInteger() && in LowerMUL()
7118 if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector())) in useSVEForFixedLengthVectorVT()
7362 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
12146 assert((SrcVT.is64BitVector() || SrcVT.is128BitVector()) && in ReconstructShuffle()
12952 if (!Extract.getOperand(0).getValueType().is128BitVector()) in constructDup()
12973 V.getOperand(0).getValueType().is128BitVector()) { in constructDup()
[all …]
|
| H A D | AArch64FastISel.cpp | 2949 VT.is128BitVector()) in fastLowerArguments()
2995 } else if (VT.is128BitVector()) { in fastLowerArguments()
|
| H A D | AArch64ISelDAGToDAG.cpp | 170 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
1641 } else if (VT.is128BitVector()) { in tryIndexedLoad()
|
| H A D | AArch64TargetTransformInfo.cpp | 3447 LT.second.is128BitVector() && (!Alignment || *Alignment < Align(16))) { in getMemoryOpCost()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/ |
| H A D | MachineValueType.h | 147 bool is128BitVector() const { in is128BitVector() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 886 assert(Node->getValueType(0).is128BitVector()); in trySelect()
1105 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector()) in trySelect()
|
| H A D | MipsSEISelLowering.cpp | 604 if (!Ty.is128BitVector()) in performORCombine()
1001 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { in performXORCombine()
2411 if (!VecTy.is128BitVector()) in lowerEXTRACT_VECTOR_ELT()
2463 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) in lowerBUILD_VECTOR()
2983 if (!ResTy.is128BitVector()) in lowerVECTOR_SHUFFLE()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3866 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || in getZeroVector()
3875 if (!Subtarget.hasSSE2() && VT.is128BitVector()) { in getZeroVector()
3997 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!"); in insert128BitVector()
4506 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && in getOnesVector()
6681 if (!VT.is128BitVector()) in LowerBuildVectorv4x32()
6765 assert(VT.is128BitVector() && "Unknown type for VShift"); in getVShift()
7085 ((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()))) { in EltsFromConsecutiveLoads()
7109 (VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector())) { in EltsFromConsecutiveLoads()
7291 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && in lowerBuildVectorAsBroadcast()
8974 assert((VT.is128BitVector() || VT.is256BitVector() || in LowerBUILD_VECTOR()
[all …]
|
| H A D | X86ISelDAGToDAG.cpp | 608 if (OpVT.is256BitVector() || OpVT.is128BitVector()) in INITIALIZE_PASS()
1059 !(VT.is128BitVector() || VT.is256BitVector())) in PreprocessISelDAG()
4597 if (NVT.is128BitVector()) in matchVPTERNLOG()
4607 if (NVT.is128BitVector()) in matchVPTERNLOG()
4627 if (NVT.is128BitVector()) in matchVPTERNLOG()
4962 unsigned Scale = CmpVT.is128BitVector() ? 4 : 2; in tryVPTESTM()
4963 unsigned SubReg = CmpVT.is128BitVector() ? X86::sub_xmm : X86::sub_ymm; in tryVPTESTM()
5300 if (NVT.is512BitVector() || NVT.is256BitVector() || NVT.is128BitVector() || in Select()
|
| H A D | X86ISelLoweringCall.cpp | 1752 else if (RegVT.is128BitVector()) in LowerFormalArguments()
2180 else if (RegVT.is128BitVector()) { in LowerCall()
|
| H A D | X86TargetTransformInfo.cpp | 3186 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || in getCmpSelInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2305 assert(VecType.is128BitVector() && "Unexpected shuffle vector type"); in LowerVECTOR_SHUFFLE()
2493 if (!SrcType.is128BitVector() || in performVECTOR_SHUFFLECombine()
2759 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
2793 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6314 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; in getZeroVector()
6998 bool is128Bits = VectorVT.is128BitVector(); in isVMOVModifiedImm()
8132 if (ST->hasNEON() && VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) { in LowerBUILD_VECTOR()
8425 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9233 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && in LowerCONCAT_VECTORS()
9515 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in AddRequiredExtensionForVMULL()
9630 assert(VT.is128BitVector() && VT.isInteger() && in LowerMUL()
10400 if (VT.is128BitVector()) { in LowerVecReduceMinMax()
12691 !N0.getValueType().is128BitVector()) in AddCombineVUZPToVPADDL()
14229 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
[all …]
|
| H A D | ARMISelDAGToDAG.cpp | 3618 assert((VT.is64BitVector() || VT.is128BitVector()) && in getVectorShuffleOpcode()
|