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Searched refs:getSubReg (Results 1 – 25 of 164) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI()
107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI()
150 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicRMW128()
151 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicRMW128()
153 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicRMW128()
154 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicRMW128()
226 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
227 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
229 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
230 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp54 Sub = MI->getOperand(0).getSubReg(); in copyHint()
56 HSub = MI->getOperand(1).getSubReg(); in copyHint()
58 Sub = MI->getOperand(1).getSubReg(); in copyHint()
60 HSub = MI->getOperand(0).getSubReg(); in copyHint()
70 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
245 DestRegOp->getSubReg() == SrcRegOp->getSubReg(); in weightCalcHelper()
H A DPeepholeOptimizer.cpp274 unsigned SrcSubReg = MI.getOperand(1).getSubReg(); in getCopySrc()
557 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
908 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
911 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
954 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
991 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
996 if (MODef.getSubReg()) in getNextRewritableSource()
1039 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1047 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
1116 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
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H A DDetectDeadLanes.cpp77 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
116 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
213 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
262 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
314 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
328 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
419 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
H A DExpandPostRAPseudos.cpp68 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); in LowerSubregToReg()
72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
H A DRegAllocFast.cpp998 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
1000 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
1033 if (MO.getSubReg() && !MO.isUndef()) { in defineLiveThroughVirtReg()
1150 if (MI.isCopy() && MI.getOperand(1).getSubReg() == 0) { in useVirtReg()
1183 if (!MO.getSubReg()) { in setPhysReg()
1190 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1358 (MO0.getSubReg() == 0 && !MO0.isUndef()); in findAndSortDefOperandIndexes()
1360 (MO1.getSubReg() == 0 && !MO1.isUndef()); in findAndSortDefOperandIndexes()
1424 if (isTiedToNotUndef(MO) || (MO.getSubReg() != 0 && !MO.isUndef())) in allocateInstruction()
1469 (MO.getSubReg() && !MO.isUndef())) { in allocateInstruction()
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H A DOptimizePHIs.cpp118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
119 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp136 unsigned getSubReg(unsigned Offset, unsigned Size) const;
165 unsigned GCNRewritePartialRegUses::getSubReg(unsigned Offset, in getSubReg() function in GCNRewritePartialRegUses
183 return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg)); in shiftSubReg()
193 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
414 return MO.getSubReg() == AMDGPU::NoSubRegister; // Whole reg used. [1] in rewriteReg()
426 const unsigned SubReg = MO.getSubReg(); in rewriteReg()
467 if (MO.isDebug() && MO.getSubReg() == 0) in rewriteReg()
469 unsigned SubReg = SubRegs[MO.getSubReg()].SubReg; in rewriteReg()
H A DGCNPreRAOptimizations.cpp120 Register SrcSubReg = I.getOperand(1).getSubReg(); in processReg()
122 if (SrcSubReg != Def.getOperand(0).getSubReg()) in processReg()
134 I.getOperand(1).setSubReg(DefSrcMO.getSubReg()); in processReg()
155 switch (I.getOperand(0).getSubReg()) { in processReg()
H A DSIFoldOperands.cpp152 TRI.getSubRegisterClass(RC, MO.getSubReg())) in getRegOpRC()
444 Old.substVirtReg(New->getReg(), New->getSubReg(), *TRI); in updateOperand()
670 !Sub->getSubReg() && TII->isFoldableCopy(*SubDef); in getRegSeqInit()
719 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
768 (UseOp->isImplicit() || UseOp->getSubReg() != AMDGPU::NoSubRegister)) in foldOperand()
789 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
891 !UseMI->getOperand(1).getSubReg()) { in foldOperand()
896 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
1036 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
1058 if (TRI->hasVectorRegisters(RC) && OpToFold.getSubReg()) { in foldOperand()
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H A DR600ExpandSpecialInstrs.cpp211 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
218 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIFrameLowering.cpp184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
256 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToMemory()
277 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToVGPRLane()
304 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromMemory()
323 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromVGPRLane()
426 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
427 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
465 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
466 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp140 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in __anon3462139c0111::EliminateFrameIndex
141 return TRI.getSubReg(Reg, Idx); in getSubReg()
244 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); in processSTQ()
245 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in processSTQ()
265 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
266 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
375 Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd); in processSTVM512()
376 Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even); in processSTVM512()
421 Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd); in processLDVM512()
422 Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even); in processLDVM512()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp33 MO.getSubReg() == SystemZ::subreg_ll32 || in getRC32()
34 MO.getSubReg() == SystemZ::subreg_l32) in getRC32()
37 MO.getSubReg() == SystemZ::subreg_lh32 || in getRC32()
38 MO.getSubReg() == SystemZ::subreg_h32) in getRC32()
113 if (MO->getSubReg()) in getRegAllocationHints()
114 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
115 if (VRRegMO->getSubReg()) in getRegAllocationHints()
116 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
H A DSystemZInstrInfo.cpp85 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64)); in splitMove()
86 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64)); in splitMove()
233 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard()
866 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64), in copyPhysReg()
867 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc); in copyPhysReg()
870 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64), in copyPhysReg()
871 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc); in copyPhysReg()
887 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64), in copyPhysReg()
890 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64), in copyPhysReg()
901 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64), in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTfrCleanup.cpp120 unsigned SubL = TRI->getSubReg(Reg, Hexagon::isub_lo); in getReg()
121 unsigned SubH = TRI->getSubReg(Reg, Hexagon::isub_hi); in getReg()
149 IMap.erase(TRI->getSubReg(DefR, isub_lo)); in updateImmMap()
150 IMap.erase(TRI->getSubReg(DefR, isub_hi)); in updateImmMap()
160 setReg(TRI->getSubReg(DefR, isub_lo), VL, IMap); in updateImmMap()
161 setReg(TRI->getSubReg(DefR, isub_hi), VH, IMap); in updateImmMap()
H A DHexagonSplitDouble.cpp258 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
319 if (!Op.getSubReg()) in profit()
323 if (MI->getOperand(1).getSubReg() != 0) in profit()
442 if (Op.getSubReg()) in isProfitable()
601 unsigned SR = Op.getSubReg(); in createHalfInstr()
647 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
650 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
660 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
672 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
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H A DHexagonRDFOpt.cpp129 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
131 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
133 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
145 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
146 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonSplitConst32AndConst64.cpp87 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
88 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DHexagonAsmPrinter.cpp137 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
466 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
467 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
543 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
544 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
555 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
556 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
569 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
570 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
H A DHexagonExpandCondsets.cpp181 Sub(Op.getSubReg()) {} in RegisterRef()
327 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
379 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
614 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
669 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
670 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
674 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
696 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split()
908 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
910 PredOp.getSubReg()); in predicateAt()
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H A DHexagonInstrInfo.cpp138 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
139 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
925 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1142 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1156 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1165 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1174 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1189 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp196 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
197 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
208 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
209 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp522 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
523 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
524 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
525 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
527 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
528 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
529 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
530 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
532 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
533 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
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