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Searched refs:getSubReg (Results 1 – 25 of 173) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp103 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI()
104 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI()
147 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicRMW128()
148 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicRMW128()
150 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicRMW128()
151 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicRMW128()
223 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
224 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
226 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
227 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
H A DPPCVSXFMAMutate.cpp213 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); in processBlock()
214 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg(); in processBlock()
215 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg(); in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp100 unsigned getSubReg(unsigned Offset, unsigned Size) const;
152 unsigned GCNRewritePartialRegUsesImpl::getSubReg(unsigned Offset, in getSubReg() function in GCNRewritePartialRegUsesImpl
170 return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg)); in shiftSubReg()
179 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
393 if (MO.getSubReg() == AMDGPU::NoSubRegister) in rewriteReg()
395 SubRegs.try_emplace(MO.getSubReg()); in rewriteReg()
421 if (MO.isDebug() && MO.getSubReg() == 0) in rewriteReg()
423 unsigned NewSubReg = SubRegs[MO.getSubReg()]; in rewriteReg()
H A DGCNPreRAOptimizations.cpp133 Register SrcSubReg = I.getOperand(1).getSubReg(); in processReg()
135 if (SrcSubReg != Def.getOperand(0).getSubReg()) in processReg()
147 I.getOperand(1).setSubReg(DefSrcMO.getSubReg()); in processReg()
168 switch (I.getOperand(0).getSubReg()) { in processReg()
277 MRI->setRegAllocationHint(Dst, 0, TRI->getSubReg(Src, AMDGPU::lo16)); in run()
282 MRI->setRegAllocationHint(Src, 0, TRI->getSubReg(Dst, AMDGPU::lo16)); in run()
H A DSIFoldOperands.cpp85 unsigned getSubReg() const { in getSubReg() function
87 return OpToFold->getSubReg(); in getSubReg()
309 TRI.getSubRegisterClass(RC, MO.getSubReg())) in getRegOpRC()
709 if (Old.getSubReg() == AMDGPU::lo16 && TRI->isSGPRReg(*MRI, New->getReg())) in updateOperand()
711 Old.substVirtReg(New->getReg(), New->getSubReg(), *TRI); in updateOperand()
843 Op.getSubReg() == CommutedOp.getSubReg())) in tryAddToFoldList()
912 if (SrcOp.getSubReg()) in lookUpCopyChain()
938 if (SrcOp.getSubReg()) { in getRegSeqInit()
1104 if (UseOp.getSubReg()) in tryToFoldACImm()
1147 if (UseOp->getSubReg() != AMDGPU::NoSubRegister && in foldOperand()
[all …]
H A DR600ExpandSpecialInstrs.cpp212 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
213 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
218 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
219 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
227 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIFrameLowering.cpp184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
256 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToMemory()
277 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToVGPRLane()
304 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromMemory()
324 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromVGPRLane()
427 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
428 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
466 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
467 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp53 Sub = MI->getOperand(0).getSubReg(); in copyHint()
55 HSub = MI->getOperand(1).getSubReg(); in copyHint()
57 Sub = MI->getOperand(1).getSubReg(); in copyHint()
59 HSub = MI->getOperand(0).getSubReg(); in copyHint()
69 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
250 DestRegOp->getSubReg() == SrcRegOp->getSubReg(); in weightCalcHelper()
H A DPeepholeOptimizer.cpp208 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
211 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
252 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
289 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
294 if (MODef.getSubReg()) in getNextRewritableSource()
337 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
345 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
408 Src.SubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource()
416 assert(MODef.getSubReg() == 0 && "cannot have subregister def in SSA"); in getNextRewritableSource()
530 unsigned SrcSubReg = MI.getOperand(1).getSubReg(); in getCopySrc()
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H A DDetectDeadLanes.cpp77 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
116 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
213 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
262 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
314 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
328 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
426 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
H A DRegAllocFast.cpp1022 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
1024 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
1057 if (MO.getSubReg() && !MO.isUndef()) { in defineLiveThroughVirtReg()
1165 if (MI.isCopy() && MI.getOperand(1).getSubReg() == 0) { in useVirtReg()
1248 if (!MO.getSubReg()) { in setPhysReg()
1255 MO.setReg(TRI->getSubReg(PhysReg, MO.getSubReg())); in setPhysReg()
1423 (MO0.getSubReg() == 0 && !MO0.isUndef()); in findAndSortDefOperandIndexes()
1425 (MO1.getSubReg() == 0 && !MO1.isUndef()); in findAndSortDefOperandIndexes()
1489 if (isTiedToNotUndef(MO) || (MO.getSubReg() != 0 && !MO.isUndef())) in allocateInstruction()
1534 (MO.getSubReg() && !MO.isUndef())) { in allocateInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp136 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in __anon3462139c0111::EliminateFrameIndex
137 return TRI.getSubReg(Reg, Idx); in getSubReg()
240 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); in processSTQ()
241 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in processSTQ()
261 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
262 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
371 Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd); in processSTVM512()
372 Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even); in processSTVM512()
417 Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd); in processLDVM512()
418 Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even); in processLDVM512()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp33 MO.getSubReg() == SystemZ::subreg_ll32 || in getRC32()
34 MO.getSubReg() == SystemZ::subreg_l32) in getRC32()
37 MO.getSubReg() == SystemZ::subreg_lh32 || in getRC32()
38 MO.getSubReg() == SystemZ::subreg_h32) in getRC32()
112 if (MO->getSubReg()) in getRegAllocationHints()
113 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
114 if (VRRegMO->getSubReg()) in getRegAllocationHints()
115 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTfrCleanup.cpp104 unsigned SubL = TRI->getSubReg(Reg, Hexagon::isub_lo); in getReg()
105 unsigned SubH = TRI->getSubReg(Reg, Hexagon::isub_hi); in getReg()
133 IMap.erase(TRI->getSubReg(DefR, isub_lo)); in updateImmMap()
134 IMap.erase(TRI->getSubReg(DefR, isub_hi)); in updateImmMap()
144 setReg(TRI->getSubReg(DefR, isub_lo), VL, IMap); in updateImmMap()
145 setReg(TRI->getSubReg(DefR, isub_hi), VH, IMap); in updateImmMap()
H A DHexagonSplitDouble.cpp252 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
313 if (!Op.getSubReg()) in profit()
317 if (MI->getOperand(1).getSubReg() != 0) in profit()
436 if (Op.getSubReg()) in isProfitable()
595 unsigned SR = Op.getSubReg(); in createHalfInstr()
641 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
644 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
650 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
654 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
666 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
[all …]
H A DHexagonRDFOpt.cpp122 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
124 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
138 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
139 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonSplitConst32AndConst64.cpp79 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
80 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DHexagonAsmPrinter.cpp135 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
464 MCRegister High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
465 MCRegister Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
541 MCRegister High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
542 MCRegister Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
553 MCRegister High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
554 MCRegister Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
567 MCRegister High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
568 MCRegister Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
H A DHexagonExpandCondsets.cpp174 Sub(Op.getSubReg()) {} in RegisterRef()
311 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
363 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
597 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
652 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
653 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
657 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
679 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split()
891 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
893 PredOp.getSubReg()); in predicateAt()
[all …]
H A DHexagonInstrInfo.cpp136 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
137 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
928 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
929 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
1144 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1145 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1159 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1168 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1177 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1192 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp142 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
144 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
146 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
148 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
150 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
H A DAArch64RegisterInfo.cpp59 RegToUseForCFI = getSubReg(Reg, AArch64::dsub); in regNeedsCFI()
1235 unsigned SubRegIdx = Use.getOperand(OpIdx).getSubReg(); in getRegAllocationHints()
1236 if (IsMulZPR && (getSubReg(Reg, SubRegIdx) - AArch64::Z0) % UseOps != in getRegAllocationHints()
1247 ((getSubReg(R, AArch64::zsub0) - AArch64::Z0) == in getRegAllocationHints()
1248 (getSubReg(R - 1, AArch64::zsub0) - AArch64::Z0) + 1)) && in getRegAllocationHints()
1260 getSubReg(VRM->getPhys(AssignedRegOp->getReg()), AArch64::zsub0) + in getRegAllocationHints()
1264 if (getSubReg(StridedOrder[I], AArch64::zsub0) == TargetStartReg) in getRegAllocationHints()
1280 unsigned FirstOpSubReg = MI.getOperand(1).getSubReg(); in getRegAllocationHints()
1297 getSubReg(VRM->getPhys(FirstOpVirtReg), FirstOpSubReg); in getRegAllocationHints()
1299 if (MCRegister R = getSubReg(Order[I], AArch64::zsub0)) in getRegAllocationHints()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp764 OP.getSubReg() == ARM::ssub_1) in modifyMixedWidthFP()
770 (OP.getSubReg() == ARM::ssub_1 || OP.getSubReg() == ARM::ssub_3)) in modifyMixedWidthFP()
772 ((OP.getSubReg() == ARM::ssub_2 || in modifyMixedWidthFP()
773 OP.getSubReg() == ARM::ssub_3) in modifyMixedWidthFP()
780 OP.getSubReg() == ARM::ssub_1) in modifyMixedWidthFP()
786 OP.getSubReg() == ARM::ssub_1) in modifyMixedWidthFP()
792 (OP.getSubReg() == ARM::ssub_1 || OP.getSubReg() == ARM::ssub_3)) in modifyMixedWidthFP()
794 ((OP.getSubReg() == ARM::ssub_2 || in modifyMixedWidthFP()
795 OP.getSubReg() == ARM::ssub_3) in modifyMixedWidthFP()
802 OP.getSubReg() == ARM::ssub_1) in modifyMixedWidthFP()
H A DARMExpandPseudoInsts.cpp521 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
522 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
523 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
524 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
526 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
527 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
528 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
529 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
531 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
532 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp196 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
197 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
208 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
209 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()

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