522     D0 = TRI->getSubReg(Reg, ARM::dsub_0);  in GetDSubRegs()
523     D1 = TRI->getSubReg(Reg, ARM::dsub_1);  in GetDSubRegs()
524     D2 = TRI->getSubReg(Reg, ARM::dsub_2);  in GetDSubRegs()
525     D3 = TRI->getSubReg(Reg, ARM::dsub_3);  in GetDSubRegs()
527     D0 = TRI->getSubReg(Reg, ARM::dsub_4);  in GetDSubRegs()
528     D1 = TRI->getSubReg(Reg, ARM::dsub_5);  in GetDSubRegs()
529     D2 = TRI->getSubReg(Reg, ARM::dsub_6);  in GetDSubRegs()
530     D3 = TRI->getSubReg(Reg, ARM::dsub_7);  in GetDSubRegs()
532     D0 = TRI->getSubReg(Reg, ARM::dsub_3);  in GetDSubRegs()
533     D1 = TRI->getSubReg(Reg, ARM::dsub_4);  in GetDSubRegs()
534     D2 = TRI->getSubReg(Reg, ARM::dsub_5);  in GetDSubRegs()
535     D3 = TRI->getSubReg(Reg, ARM::dsub_6);  in GetDSubRegs()
537     D0 = TRI->getSubReg(Reg, ARM::dsub_0);  in GetDSubRegs()
538     D1 = TRI->getSubReg(Reg, ARM::dsub_2);  in GetDSubRegs()
539     D2 = TRI->getSubReg(Reg, ARM::dsub_4);  in GetDSubRegs()
540     D3 = TRI->getSubReg(Reg, ARM::dsub_6);  in GetDSubRegs()
543     D0 = TRI->getSubReg(Reg, ARM::dsub_1);  in GetDSubRegs()
544     D1 = TRI->getSubReg(Reg, ARM::dsub_3);  in GetDSubRegs()
545     D2 = TRI->getSubReg(Reg, ARM::dsub_5);  in GetDSubRegs()
546     D3 = TRI->getSubReg(Reg, ARM::dsub_7);  in GetDSubRegs()
587     Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);  in ExpandVLD()
890   MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags);  in ExpandMQQPRLoadStore()
891   MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags);  in ExpandMQQPRLoadStore()
892   MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags);  in ExpandMQQPRLoadStore()
893   MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags);  in ExpandMQQPRLoadStore()
896     MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags);  in ExpandMQQPRLoadStore()
897     MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags);  in ExpandMQQPRLoadStore()
898     MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags);  in ExpandMQQPRLoadStore()
899     MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags);  in ExpandMQQPRLoadStore()
1512         unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);  in CMSESaveClearFPRegsV8()
1928     Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);  in addExclusiveRegPair()
1929     Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);  in addExclusiveRegPair()
1954   Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);  in ExpandCMP_SWAP_64()
1955   Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);  in ExpandCMP_SWAP_64()
1956   Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);  in ExpandCMP_SWAP_64()
1957   Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);  in ExpandCMP_SWAP_64()
2793       Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);  in ExpandMI()
2794       Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);  in ExpandMI()
2825       Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);  in ExpandMI()
2826       Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);  in ExpandMI()
3229               .addReg(TRI->getSubReg(PairReg, ARM::gsub_0),  in ExpandMI()
3231               .addReg(TRI->getSubReg(PairReg, ARM::gsub_1),  in ExpandMI()