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Searched refs:getOpcode (Results 1 – 25 of 1038) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h41 return isPreISelGenericOpcode(MI->getOpcode()); in classof()
87 switch (MI->getOpcode()) { in classof()
117 return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD; in classof()
125 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD || in classof()
126 MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD; in classof()
134 switch (MI->getOpcode()) { in classof()
149 return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD; in classof()
157 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD; in classof()
177 return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE; in classof()
193 switch (MI->getOpcode()) { in classof()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MacroFusion.cpp24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
39 switch (FirstMI->getOpcode()) { in isArithmeticBccPair()
73 if (SecondMI.getOpcode() != AArch64::CBZW && in isArithmeticCbzPair()
74 SecondMI.getOpcode() != AArch64::CBZX && in isArithmeticCbzPair()
75 SecondMI.getOpcode() != AArch64::CBNZW && in isArithmeticCbzPair()
76 SecondMI.getOpcode() != AArch64::CBNZX) in isArithmeticCbzPair()
83 switch (FirstMI->getOpcode()) { in isArithmeticCbzPair()
124 switch (SecondMI.getOpcode()) { in isAESPair()
128 return FirstMI == nullptr || FirstMI->getOpcode() == AArch64::AESErr; in isAESPair()
132 return FirstMI == nullptr || FirstMI->getOpcode() == AArch64::AESDrr; in isAESPair()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp29 switch (MI.getOpcode()) { in isConstantInstr()
51 switch (MI.getOpcode()) { in isInlineAsmDefInstr()
66 return MI.getOpcode() == SPIRV::OpTypeForwardPointer; in isTypeDeclInstr()
71 switch (MI.getOpcode()) { in isDecorationInstr()
84 switch (MI.getOpcode()) { in isHeaderInstr()
106 switch (MI.getOpcode()) { in canUseFastMathFlags()
125 switch (MI.getOpcode()) { in canUseNSW()
142 switch (MI.getOpcode()) { in canUseNUW()
194 if (MI->getOpcode() == SPIRV::OpBranch) { in analyzeBranch()
197 } else if (MI->getOpcode() == SPIRV::OpBranchConditional) { in analyzeBranch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp86 if (Addr.getOpcode() == ISD::FrameIndex) in INITIALIZE_PASS()
88 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in INITIALIZE_PASS()
89 Addr.getOpcode() == ISD::TargetGlobalAddress || in INITIALIZE_PASS()
90 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in INITIALIZE_PASS()
150 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in selectADDRzii()
151 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRzii()
152 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in selectADDRzii()
181 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in selectADDRzi()
182 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRzi()
183 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in selectADDRzi()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC && in INITIALIZE_PASS()
88 Hi.getOpcode() != RISCV::PseudoMovAddr) in INITIALIZE_PASS()
93 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; in INITIALIZE_PASS()
101 if (Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
111 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
116 if (Hi.getOpcode() == RISCV::LUI || Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
122 assert(Hi.getOpcode() == RISCV::AUIPC); in INITIALIZE_PASS()
150 if (Hi.getOpcode() != RISCV::AUIPC) in foldOffset()
185 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); in foldLargeOffset()
195 if (OffsetTail.getOpcode() == RISCV::ADDI || in foldLargeOffset()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h208 inline unsigned getOpcode() const;
668 unsigned getOpcode() const { return (unsigned)NodeType; }
721 bool isVPOpcode() const { return ISD::isVPOpcode(getOpcode()); }
910 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
1182 inline unsigned SDValue::getOpcode() const {
1183 return Node->getOpcode();
1317 return N->getOpcode() == ISD::ADDRSPACECAST;
1428 switch (getOpcode()) {
1449 switch (N->getOpcode()) {
1506 assert(getOpcode() == ISD::ATOMIC_LOAD && "Only used for atomic loads.");
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp159 if (MI.getOpcode() != BPF::XADDW && in processAtomicInsts()
160 MI.getOpcode() != BPF::XADDD && in processAtomicInsts()
161 MI.getOpcode() != BPF::XADDW32) in processAtomicInsts()
188 if (MI.getOpcode() != BPF::XFADDW32 && MI.getOpcode() != BPF::XFADDD && in processAtomicInsts()
189 MI.getOpcode() != BPF::XFANDW32 && MI.getOpcode() != BPF::XFANDD && in processAtomicInsts()
190 MI.getOpcode() != BPF::XFXORW32 && MI.getOpcode() != BPF::XFXORD && in processAtomicInsts()
191 MI.getOpcode() != BPF::XFORW32 && MI.getOpcode() != BPF::XFORD) in processAtomicInsts()
199 switch (MI.getOpcode()) { in processAtomicInsts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600EmitClauseMarkers.cpp38 switch (MI.getOpcode()) { in OccupiedDwords()
52 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
55 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
56 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI.getOpcode())) in isALU()
73 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
75 switch (MI.getOpcode()) { in isALU()
89 switch (MI.getOpcode()) { in IsTrivialInst()
119 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != R600::DOT_4) in SubstituteKCacheBank()
125 (TII->isALUInstr(MI.getOpcode()) || MI.getOpcode() == R600::DOT_4) && in SubstituteKCacheBank()
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H A DR600InstrInfo.cpp37 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
139 if (isALUInstr(MI.getOpcode())) in canBeConsideredALU()
141 if (isVector(MI) || isCubeOp(MI.getOpcode())) in canBeConsideredALU()
143 switch (MI.getOpcode()) { in canBeConsideredALU()
163 return isTransOnly(MI.getOpcode()); in isTransOnly()
171 return isVectorOnly(MI.getOpcode()); in isVectorOnly()
185 usesVertexCache(MI.getOpcode()); in usesVertexCache()
195 usesVertexCache(MI.getOpcode())) || in usesTextureCache()
196 usesTextureCache(MI.getOpcode()); in usesTextureCache()
218 if (!isALUInstr(MI.getOpcode())) { in readsLDSSrcReg()
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H A DR600Packetizer.cpp67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
93 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
94 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); in substitutePV()
166 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
168 if (MI.getOpcode() == R600::GROUP_BARRIER) in isSoloInstruction()
172 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
182 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), in isLegalToPacketizeTogether()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGStackify.cpp304 if (MI.getOpcode() == WebAssembly::LOOP) { in placeBlockMarker()
318 if (MI.getOpcode() == WebAssembly::BLOCK || in placeBlockMarker()
319 MI.getOpcode() == WebAssembly::TRY) { in placeBlockMarker()
330 if (MI.getOpcode() == WebAssembly::END_BLOCK || in placeBlockMarker()
331 MI.getOpcode() == WebAssembly::END_LOOP || in placeBlockMarker()
332 MI.getOpcode() == WebAssembly::END_TRY) in placeBlockMarker()
366 if (MI.getOpcode() == WebAssembly::LOOP || in placeBlockMarker()
367 MI.getOpcode() == WebAssembly::TRY) in placeBlockMarker()
375 if (MI.getOpcode() == WebAssembly::END_LOOP || in placeBlockMarker()
376 MI.getOpcode() == WebAssembly::END_TRY) { in placeBlockMarker()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp102 while (MI && MI->getOpcode() == TargetOpcode::COPY && in INITIALIZE_PASS_DEPENDENCY()
124 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) { in findLoopComponents()
128 if (T.getOpcode() == ARM::t2LoopEndDec && in findLoopComponents()
149 if (LoopEnd->getOpcode() == ARM::t2LoopEndDec) in findLoopComponents()
154 if (!LoopDec || LoopDec->getOpcode() != ARM::t2LoopDec) { in findLoopComponents()
163 if (!LoopPhi || LoopPhi->getOpcode() != TargetOpcode::PHI || in findLoopComponents()
176 if (!LoopStart || (LoopStart->getOpcode() != ARM::t2DoLoopStart && in findLoopComponents()
177 LoopStart->getOpcode() != ARM::t2WhileLoopSetup && in findLoopComponents()
178 LoopStart->getOpcode() != ARM::t2WhileLoopStartLR)) { in findLoopComponents()
189 assert(MI->getOpcode() == ARM::t2WhileLoopSetup && in RevertWhileLoopSetup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp136 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
220 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
221 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
222 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
229 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
230 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
257 switch (MI.getOpcode()) { in canCompareBeNewValueJump()
295 if (def->getOpcode() == TargetOpcode::COPY) in canCompareBeNewValueJump()
347 switch (MI->getOpcode()) { in getNewValueJumpOpcode()
429 switch (MI.getOpcode()) { in isNewValueJumpCandidate()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp119 if (Addr.getOpcode() == ISD::OR && in INITIALIZE_PASS()
120 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) { in INITIALIZE_PASS()
169 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || in selectAddrRiSpls()
170 Addr.getOpcode() == ISD::TargetGlobalAddress)) in selectAddrRiSpls()
174 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode()); in selectAddrRiSpls()
198 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) in selectAddrRiSpls()
251 if (Addr.getOpcode() == ISD::FrameIndex) in selectAddrRr()
255 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || in selectAddrRr()
256 Addr.getOpcode() == ISD::TargetGlobalAddress)) in selectAddrRr()
260 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode()); in selectAddrRr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp84 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeImm()
94 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeS9()
98 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB && in SelectAddrModeS9()
100 if (Addr.getOpcode() == ISD::FrameIndex) { in SelectAddrModeS9()
114 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeS9()
121 if (Base.getOpcode() == ISD::FrameIndex) { in SelectAddrModeS9()
138 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeFar()
143 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeFar()
161 if (Addr.getOpcode() == ISD::ADD) { in SelectFrameADDR_ri()
177 switch (N->getOpcode()) { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp116 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
117 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
125 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
126 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
177 unsigned Opc = slot->getOpcode(); in findDelayInstr()
186 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
187 || J->getOpcode() == SP::RESTOREri) { in findDelayInstr()
271 unsigned Opcode = candidate->getOpcode(); in delayHasHazard()
297 switch(MI->getOpcode()) { in insertCallDefsUses()
335 if (MO.isImplicit() && MI->getOpcode() == SP::RETL) in insertDefsUses()
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H A DSparcISelDAGToDAG.cpp96 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
97 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRri()
98 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRri()
101 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
117 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
122 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
134 if (Addr.getOpcode() == ISD::FrameIndex) return false; in SelectADDRrr()
135 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRrr()
136 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRrr()
137 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRrr()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DOperator.h42 unsigned getOpcode() const { in getOpcode() function
44 return I->getOpcode(); in getOpcode()
45 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
50 static unsigned getOpcode(const Value *V) { in getOpcode() function
52 return I->getOpcode(); in getOpcode()
54 return CE->getOpcode(); in getOpcode()
127 return I->getOpcode() == Instruction::Add || in classof()
128 I->getOpcode() == Instruction::Sub || in classof()
129 I->getOpcode() == Instruction::Mul || in classof()
130 I->getOpcode() == Instruction::Shl; in classof()
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h56 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
60 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
64 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
68 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
72 return Info->get(Inst.getOpcode()).isCall(); in isCall()
76 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
80 return Info->get(Inst.getOpcode()).isTerminator(); in isTerminator()
91 return Info->get(Inst.getOpcode()).hasDefOfPhysReg(Inst, PC, MCRI); in mayAffectControlFlow()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTLSDynamicCall.cpp68 bool IsTLSTPRelMI = MI.getOpcode() == PPC::GETtlsTpointer32AIX; in processBlock()
69 bool IsTLSLDAIXMI = (MI.getOpcode() == PPC::TLSLDAIX8 || in processBlock()
70 MI.getOpcode() == PPC::TLSLDAIX); in processBlock()
72 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
73 MI.getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
74 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
75 MI.getOpcode() != PPC::ADDItlsldLADDR32 && in processBlock()
76 MI.getOpcode() != PPC::TLSGDAIX && in processBlock()
77 MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL && in processBlock()
83 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) in processBlock()
[all …]
H A DPPCBranchSelector.cpp142 if (TII->isPrefixed(MI.getOpcode())) { in ComputeBlockSizes()
329 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
331 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
334 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
335 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
358 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
369 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
372 } else if (I->getOpcode() == PPC::BCn) { in runOnMachineFunction()
375 } else if (I->getOpcode() == PPC::BDNZ) { in runOnMachineFunction()
377 } else if (I->getOpcode() == PPC::BDNZ8) { in runOnMachineFunction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp133 if (MI->getOpcode() == TargetOpcode::G_LOAD || in isGprbTwoInstrUnalignedLoadOrStore()
134 MI->getOpcode() == TargetOpcode::G_STORE) { in isGprbTwoInstrUnalignedLoadOrStore()
167 if (NonCopyInstr->getOpcode() == TargetOpcode::COPY && in addDefUses()
189 while (Ret->getOpcode() == TargetOpcode::COPY && in skipCopiesOutgoing()
203 while (Ret->getOpcode() == TargetOpcode::COPY && in skipCopiesIncoming()
211 assert(isAmbiguous(MI->getOpcode()) && in AmbiguousRegDefUseContainer()
216 if (MI->getOpcode() == TargetOpcode::G_LOAD) in AmbiguousRegDefUseContainer()
219 if (MI->getOpcode() == TargetOpcode::G_STORE) in AmbiguousRegDefUseContainer()
229 if (MI->getOpcode() == TargetOpcode::G_SELECT) { in AmbiguousRegDefUseContainer()
236 if (MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) in AmbiguousRegDefUseContainer()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DynAllocaExpander.cpp81 assert(MI->getOpcode() == X86::DYN_ALLOCA_32 || in getDynAllocaAmount()
82 MI->getOpcode() == X86::DYN_ALLOCA_64); in getDynAllocaAmount()
89 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) || in getDynAllocaAmount()
112 switch (MI.getOpcode()) { in isPushPop()
154 if (MI.getOpcode() == X86::DYN_ALLOCA_32 || in computeLowerings()
155 MI.getOpcode() == X86::DYN_ALLOCA_64) { in computeLowerings()
174 } else if (MI.getOpcode() == X86::ADJCALLSTACKUP32 || in computeLowerings()
175 MI.getOpcode() == X86::ADJCALLSTACKUP64) { in computeLowerings()
177 } else if (MI.getOpcode() == X86::ADJCALLSTACKDOWN32 || in computeLowerings()
178 MI.getOpcode() == X86::ADJCALLSTACKDOWN64) { in computeLowerings()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanSLP.cpp84 unsigned Opcode = OriginalInstr->getOpcode(); in areVectorizable()
88 return I->getOpcode() == Opcode && in areVectorizable()
120 if (VPI->getOpcode() == Instruction::Load && in areVectorizable()
167 cast<VPInstruction>(Values[0])->getOpcode()); in areCommutative()
175 switch (VPI->getOpcode()) { in getOperands()
191 static std::optional<unsigned> getOpcode(ArrayRef<VPValue *> Values) { in getOpcode() function
192 unsigned Opcode = cast<VPInstruction>(Values[0])->getOpcode(); in getOpcode()
194 return cast<VPInstruction>(V)->getOpcode() != Opcode; in getOpcode()
204 if (A->getOpcode() != B->getOpcode()) in areConsecutiveOrMatch()
207 if (A->getOpcode() != Instruction::Load && in areConsecutiveOrMatch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp272 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
277 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
719 switch (StoreVal.getOpcode()) { in getStoreSource()
969 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
977 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
978 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
985 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || in isSetCCEquivalent()
1042 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
1059 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
1068 (LD->getOperand(2).getOpcode() != ISD::TargetConstant || in canSplitIdx()
[all …]

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