87   if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC &&  in INITIALIZE_PASS()
88       Hi.getOpcode() != RISCV::PseudoMovAddr)  in INITIALIZE_PASS()
93       Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI;  in INITIALIZE_PASS()
101   if (Hi.getOpcode() == RISCV::PseudoMovAddr) {  in INITIALIZE_PASS()
111     if (Lo->getOpcode() != RISCV::ADDI)  in INITIALIZE_PASS()
116   if (Hi.getOpcode() == RISCV::LUI || Hi.getOpcode() == RISCV::PseudoMovAddr) {  in INITIALIZE_PASS()
122     assert(Hi.getOpcode() == RISCV::AUIPC);  in INITIALIZE_PASS()
150   if (Hi.getOpcode() != RISCV::AUIPC)  in foldOffset()
185   assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");  in foldLargeOffset()
195   if (OffsetTail.getOpcode() == RISCV::ADDI ||  in foldLargeOffset()
196       OffsetTail.getOpcode() == RISCV::ADDIW) {  in foldLargeOffset()
215     if (OffsetLui.getOpcode() != RISCV::LUI ||  in foldLargeOffset()
222     if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW)  in foldLargeOffset()
233   } else if (OffsetTail.getOpcode() == RISCV::LUI) {  in foldLargeOffset()
260   assert((TailShXAdd.getOpcode() == RISCV::SH1ADD ||  in foldShiftedOffset()
261           TailShXAdd.getOpcode() == RISCV::SH2ADD ||  in foldShiftedOffset()
262           TailShXAdd.getOpcode() == RISCV::SH3ADD) &&  in foldShiftedOffset()
276   if (OffsetTail.getOpcode() != RISCV::ADDI)  in foldShiftedOffset()
287   switch (TailShXAdd.getOpcode()) {  in foldShiftedOffset()
314   switch (Tail.getOpcode()) {  in detectAndFoldOffset()
327       if (TailTail.getOpcode() == RISCV::ADDI) {  in detectAndFoldOffset()
382     switch (UseMI.getOpcode()) {  in foldIntoMemoryOps()
485   if (Hi.getOpcode() == RISCV::PseudoMovAddr) {  in foldIntoMemoryOps()
491   if (Hi.getOpcode() != RISCV::AUIPC)  in foldIntoMemoryOps()
497     if (UseMI.getOpcode() == RISCV::INLINEASM ||  in foldIntoMemoryOps()
498         UseMI.getOpcode() == RISCV::INLINEASM_BR) {  in foldIntoMemoryOps()