Lines Matching refs:getOpcode
272 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
277 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
719 switch (StoreVal.getOpcode()) { in getStoreSource()
969 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
977 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
978 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
985 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || in isSetCCEquivalent()
1042 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
1059 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
1068 (LD->getOperand(2).getOpcode() != ISD::TargetConstant || in canSplitIdx()
1086 if (N0.getOpcode() != ISD::ADD) in reassociationCanBreakAddressingModePattern()
1093 if ((N1.getOpcode() == ISD::VSCALE || in reassociationCanBreakAddressingModePattern()
1094 ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) && in reassociationCanBreakAddressingModePattern()
1095 N1.getOperand(0).getOpcode() == ISD::VSCALE && in reassociationCanBreakAddressingModePattern()
1098 int64_t ScalableOffset = N1.getOpcode() == ISD::VSCALE in reassociationCanBreakAddressingModePattern()
1101 (N1.getOpcode() == ISD::SHL in reassociationCanBreakAddressingModePattern()
1166 if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA)) in reassociationCanBreakAddressingModePattern()
1198 if (N0.getOpcode() != Opc) in reassociateOpsCommutative()
1206 if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() && in reassociateOpsCommutative()
1271 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC && in reassociateOpsCommutative()
1272 N01->getOpcode() == ISD::SETCC) { in reassociateOpsCommutative()
1316 if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc && in reassociateReduction()
1442 unsigned Opc = Op.getOpcode(); in PromoteOperand()
1509 unsigned Opc = Op.getOpcode(); in PromoteIntBinOp()
1577 unsigned Opc = Op.getOpcode(); in PromoteIntShiftOp()
1610 if (Op && Op.getOpcode() != ISD::DELETED_NODE) in PromoteIntShiftOp()
1626 unsigned Opc = Op.getOpcode(); in PromoteExtend()
1639 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); in PromoteExtend()
1657 unsigned Opc = Op.getOpcode(); in PromoteLoad()
1799 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1800 RV.getOpcode() != ISD::DELETED_NODE && in Run()
1818 if (RV.getOpcode() != ISD::EntryToken) in Run()
1835 switch (N->getOpcode()) { in visit()
2008 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
2011 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
2012 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
2024 switch (N->getOpcode()) { in combine()
2053 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) { in combine()
2060 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, in combine()
2106 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) in visitTokenFactor()
2135 switch (Op.getOpcode()) { in visitTokenFactor()
2221 switch (CurNode->getOpcode()) { in visitTokenFactor()
2306 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
2353 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
2362 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
2393 if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) in foldSelectWithIdentityConstant()
2401 unsigned Opcode = N->getOpcode(); in foldSelectWithIdentityConstant()
2426 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && in foldBinOpIntoSelect()
2430 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect()
2436 if (TLI.isCommutativeBinOp(BO->getOpcode())) in foldBinOpIntoSelect()
2446 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { in foldBinOpIntoSelect()
2462 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) in foldBinOpIntoSelect()
2530 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubBoolOfMaskedVal()
2536 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal()
2540 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2588 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubOfSignBit()
2593 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit()
2597 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2673 if (N0.getOpcode() == ISD::SUB) { in visitADDLike()
2690 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
2791 return DAG.getNode(N1.getOpcode(), DL, VT, B, C); in visitADDLike()
2802 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2823 if (N0.getOpcode() == ISD::ADD) { in visitADDLike()
2842 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLike()
2853 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitADDLike()
2978 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2985 if (N0.getOpcode() == ISD::ADD && in visitADD()
2986 N0.getOperand(1).getOpcode() == ISD::VSCALE && in visitADD()
2987 N1.getOpcode() == ISD::VSCALE) { in visitADD()
2995 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitADD()
2996 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
3004 if (N0.getOpcode() == ISD::ADD && in visitADD()
3005 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && in visitADD()
3006 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
3018 unsigned Opcode = N->getOpcode(); in visitADDSAT()
3065 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
3070 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { in getAsCarry()
3089 if (V.getOpcode() != ISD::UADDO_CARRY && V.getOpcode() != ISD::USUBO_CARRY && in getAsCarry()
3090 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) in getAsCarry()
3094 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) in getAsCarry()
3113 if (N1.getOpcode() == ISD::ZERO_EXTEND) in foldAddSubMasked1()
3116 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) in foldAddSubMasked1()
3121 if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE) in foldAddSubMasked1()
3154 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLikeCommutative()
3163 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) { in visitADDLikeCommutative()
3180 if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 && in visitADDLikeCommutative()
3191 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
3199 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
3209 if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
3267 if (V.getOpcode() != ISD::XOR) in extractBooleanFlip()
3300 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO()
3313 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitADDO()
3355 if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
3385 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
3469 if (Carry1.getOpcode() != ISD::UADDO) in combineUADDO_CARRYDiamond()
3478 if (Carry0.getOpcode() == ISD::UADDO_CARRY && in combineUADDO_CARRYDiamond()
3481 } else if (Carry0.getOpcode() == ISD::UADDO && in combineUADDO_CARRYDiamond()
3565 unsigned Opcode = Carry0.getOpcode(); in combineCarryDiamond()
3566 if (Opcode != Carry1.getOpcode()) in combineCarryDiamond()
3623 if (N->getOpcode() == ISD::AND) in combineCarryDiamond()
3645 if ((N0.getOpcode() == ISD::ADD || in visitUADDO_CARRYLike()
3646 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitUADDO_CARRYLike()
3739 if (N->getOpcode() != ISD::SUB || in foldSubToUSubSat()
3749 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in foldSubToUSubSat()
3758 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3768 if (Op1.getOpcode() == ISD::TRUNCATE && in foldSubToUSubSat()
3769 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
3773 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) in foldSubToUSubSat()
3776 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) in foldSubToUSubSat()
3803 if (N->getOpcode() == ISD::FREEZE && N.hasOneUse()) in visitSUB()
3840 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3843 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3864 if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() && in visitSUB()
3872 if (N1S && N1S.getOpcode() == ISD::SUB && in visitSUB()
3883 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitSUB()
3887 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
3891 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
3895 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
3899 if (N0.getOpcode() == ISD::ADD) { in visitSUB()
3906 if (N1.getOpcode() == ISD::ADD) { in visitSUB()
3913 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3920 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3993 N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSUB()
3999 if (N1.getOpcode() == ISD::ADD && N1.hasOneUse() && in visitSUB()
4006 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSUB()
4012 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSUB()
4021 if (N1.getOpcode() == ISD::ZERO_EXTEND && in visitSUB()
4046 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
4056 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { in visitSUB()
4062 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { in visitSUB()
4070 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4082 if (N1.getOpcode() == ISD::SHL) { in visitSUB()
4089 if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) && in visitSUB()
4133 unsigned Opcode = N->getOpcode(); in visitSUBSAT()
4205 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
4249 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
4300 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); in visitMULFIX()
4496 if (!UseVP && N0.getOpcode() == ISD::VSCALE && NC1) { in visitMUL()
4504 if (!UseVP && N0.getOpcode() == ISD::STEP_VECTOR && in visitMUL()
4539 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); in visitMUL()
4595 unsigned Opcode = Node->getOpcode(); in useDivRem()
4629 if (User == Node || User->getOpcode() == ISD::DELETED_NODE || in useDivRem()
4635 unsigned UserOpc = User->getOpcode(); in useDivRem()
4665 unsigned Opc = N->getOpcode(); in simplifyDivRem()
4925 if (N1.getOpcode() == ISD::SHL) { in visitUDIVLike()
4963 unsigned Opcode = N->getOpcode(); in visitREM()
5008 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
5192 unsigned Opcode = N->getOpcode(); in visitAVG()
5267 unsigned Opcode = N->getOpcode(); in visitABD()
5341 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
5351 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
5456 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
5479 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitMULO()
5521 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) in isSaturatingMinMax()
5542 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) { in isSaturatingMinMax()
5562 switch (N0.getOpcode()) { in isSaturatingMinMax()
5567 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
5578 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
5623 if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT) in PerformMinMaxFpToSatCombine()
5646 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) || in PerformUMinFpToSatCombine()
5647 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT) in PerformUMinFpToSatCombine()
5679 unsigned Opcode = N->getOpcode(); in visitIMINMAX()
5709 bool IsSatBroken = Opcode == ISD::UMIN && N0.getOpcode() == ISD::SMAX; in visitIMINMAX()
5763 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5764 unsigned HandOpcode = N0.getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5766 assert(HandOpcode == N1.getOpcode() && "Bad input!"); in hoistLogicOpWithSameOpcodeHands()
6154 (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && in foldAndOrOfSETCC()
6160 if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || in foldAndOrOfSETCC()
6249 bool IsOr = (LogicOp->getOpcode() == ISD::OR); in foldAndOrOfSETCC()
6256 getMinMaxOpcodeForFP(Operand1, Operand2, CC, LogicOp->getOpcode(), in foldAndOrOfSETCC()
6271 CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) && in foldAndOrOfSETCC()
6349 if (T.getOpcode() != ISD::AND) in combineSelectAsExtAnd()
6379 if (N1.getOpcode() == ISD::ADD) in visitANDLike()
6383 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
6555 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && in SearchForAndLoads()
6564 switch(Op.getOpcode()) { in SearchForAndLoads()
6588 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
6661 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
6690 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
6710 assert(N->getOpcode() == ISD::AND); in unfoldExtremeBitClearingToShifts()
6726 OuterShift = M->getOpcode(); in unfoldExtremeBitClearingToShifts()
6762 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); in combineShiftAnd1ToBitTest()
6766 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
6783 if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6788 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6862 unsigned LogicOpcode = N->getOpcode(); in foldLogicOfShifts()
6870 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6871 if (LogicOp.getOpcode() != LogicOpcode || in foldLogicOfShifts()
6883 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6887 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6910 unsigned LogicOpcode = N->getOpcode(); in foldLogicTreeOfShifts()
6913 if (LeftHand.getOpcode() != LogicOpcode || in foldLogicTreeOfShifts()
6914 RightHand.getOpcode() != LogicOpcode) in foldLogicTreeOfShifts()
7034 if (N0.getOpcode() == ISD::OR && in visitAND()
7038 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
7060 if (ISD::isExtOpcode(N0.getOpcode())) { in visitAND()
7061 unsigned ExtOpc = N0.getOpcode(); in visitAND()
7063 if (N0Op0.getOpcode() == ISD::AND && in visitAND()
7083 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
7085 N0.getOperand(0).getOpcode() == ISD::LOAD && in visitAND()
7087 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
7089 cast<LoadSDNode>((N0.getOpcode() == ISD::LOAD) ? N0 : N0.getOperand(0)); in visitAND()
7187 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && in visitAND()
7188 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitAND()
7230 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector()) in visitAND()
7247 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
7263 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { in visitAND()
7266 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
7269 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && in visitAND()
7305 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { in visitAND()
7324 if (LHS->getOpcode() != ISD::SIGN_EXTEND) in visitAND()
7370 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
7372 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
7374 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7387 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7397 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
7399 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
7413 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7424 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7481 unsigned Opc = N.getOpcode(); in isBSwapHWordElement()
7486 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement()
7563 if (N.getOpcode() == ISD::OR) in isBSwapHWordPair()
7567 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
7585 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && in matchBSwapHWordOrAndAnd()
7589 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) in matchBSwapHWordOrAndAnd()
7603 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
7654 } else if (N0.getOpcode() == ISD::OR) { in MatchBSwapHWord()
7700 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in visitORLike()
7726 if (N0.getOpcode() == ISD::AND && in visitORLike()
7727 N1.getOpcode() == ISD::AND && in visitORLike()
7747 if (V->getOpcode() == ISD::ZERO_EXTEND || V->getOpcode() == ISD::TRUNCATE) in visitORCommutative()
7753 if (N0Resized.getOpcode() == ISD::AND) { in visitORCommutative()
7796 if (V->getOpcode() == ISD::ZERO_EXTEND) in visitORCommutative()
7802 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
7808 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
7971 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() && in visitOR()
7987 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
8019 if (Op.getOpcode() == ISD::AND && in stripConstantMask()
8031 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
8066 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
8080 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
8081 ExtractFrom.getOpcode() == ISD::ADD && in extractShiftForRotate()
8097 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; in extractShiftForRotate()
8098 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) in extractShiftForRotate()
8105 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
8106 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
8111 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
8234 if (Neg.getOpcode() != ISD::SUB) in matchRotateSub()
8269 (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) in matchRotateSub()
8281 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { in matchRotateSub()
8354 if (Op.getOpcode() != BinOpc) in MatchFunnelPosNeg()
8381 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && in MatchFunnelPosNeg()
8420 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
8466 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
8470 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
8477 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
8523 if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR) in MatchRotate()
8592 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
8593 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
8594 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
8595 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
8596 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
8597 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
8598 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
8599 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
8688 (Op.getOpcode() != ISD::LOAD || !Op.getValueType().isVector())) in calculateByteProvider()
8693 if (Op.getOpcode() != ISD::LOAD && VectorIndex.has_value()) in calculateByteProvider()
8703 switch (Op.getOpcode()) { in calculateByteProvider()
8749 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
8851 switch (Value.getOpcode()) { in stripTruncAndExt()
8944 if (Trunc.getOpcode() != ISD::TRUNCATE) in mergeTruncStores()
8950 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
9105 assert(N->getOpcode() == ISD::OR && in MatchLoadCombine()
9304 assert(N->getOpcode() == ISD::XOR); in unfoldMaskedMerge()
9316 if (And.getOpcode() != ISD::AND || !And.hasOneUse()) in unfoldMaskedMerge()
9319 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) in unfoldMaskedMerge()
9453 unsigned N0Opcode = N0.getOpcode(); in visitXOR()
9527 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && in visitXOR()
9534 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && in visitXOR()
9551 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { in visitXOR()
9590 if (N0Opcode == N1.getOpcode()) in visitXOR()
9625 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
9631 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic()
9638 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic()
9715 switch (LHS.getOpcode()) { in visitShiftByConstant()
9723 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
9732 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || in visitShiftByConstant()
9733 BinOpLHSVal.getOpcode() == ISD::SRA || in visitShiftByConstant()
9734 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
9736 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
9737 BinOpLHSVal.getOpcode() == ISD::SELECT; in visitShiftByConstant()
9749 N->getOpcode(), DL, VT, {LHS.getOperand(1), N->getOperand(1)})) { in visitShiftByConstant()
9750 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant()
9752 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
9759 assert(N->getOpcode() == ISD::TRUNCATE); in distributeTruncateThroughAnd()
9760 assert(N->getOperand(0).getOpcode() == ISD::AND); in distributeTruncateThroughAnd()
9810 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); in visitRotate()
9824 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
9825 N1.getOperand(0).getOpcode() == ISD::AND) { in visitRotate()
9827 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); in visitRotate()
9830 unsigned NextOp = N0.getOpcode(); in visitRotate()
9839 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()
9853 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), in visitRotate()
9885 if (N0.getOpcode() == ISD::AND) { in visitSHL()
9890 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
9909 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
9910 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSHL()
9916 if (N0.getOpcode() == ISD::SHL) { in visitSHL()
9945 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
9946 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
9947 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
9948 N0.getOperand(0).getOpcode() == ISD::SHL) { in visitSHL()
9978 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); in visitSHL()
9988 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
9989 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
10010 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
10034 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff); in visitSHL()
10042 if (N0.getOpcode() == ISD::SRL && in visitSHL()
10070 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && in visitSHL()
10081 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && in visitSHL()
10090 if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint()) in visitSHL()
10092 return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags); in visitSHL()
10099 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitSHL()
10100 N0.getOperand(0).getOpcode() == ISD::ADD && in visitSHL()
10106 if (SDValue ExtC = DAG.FoldConstantArithmetic(N0.getOpcode(), DL, VT, in visitSHL()
10110 SDValue ExtX = DAG.getNode(N0.getOpcode(), DL, VT, Add.getOperand(0)); in visitSHL()
10118 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) { in visitSHL()
10132 if (((N1.getOpcode() == ISD::CTTZ && in visitSHL()
10134 N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in visitSHL()
10149 if (N0.getOpcode() == ISD::VSCALE && N1C) { in visitSHL()
10157 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitSHL()
10175 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
10186 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
10193 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH()
10194 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; in combineShiftToMULH()
10204 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { in combineShiftToMULH()
10235 if (LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
10279 bool IsSigned = N->getOpcode() == ISD::SRA; in combineShiftToMULH()
10286 unsigned Opcode = N->getOpcode(); in foldBitOrderCrossLogicOp()
10293 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) { in foldBitOrderCrossLogicOp()
10299 if (OldLHS.getOpcode() == Opcode && OldRHS.getOpcode() == Opcode) { in foldBitOrderCrossLogicOp()
10300 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), in foldBitOrderCrossLogicOp()
10304 if (OldLHS.getOpcode() == Opcode && OldLHS.hasOneUse()) { in foldBitOrderCrossLogicOp()
10306 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), in foldBitOrderCrossLogicOp()
10310 if (OldRHS.getOpcode() == Opcode && OldRHS.hasOneUse()) { in foldBitOrderCrossLogicOp()
10312 return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder, in foldBitOrderCrossLogicOp()
10351 if (N0.getOpcode() == ISD::SRA) { in visitSRA()
10368 if (N1.getOpcode() == ISD::BUILD_VECTOR) in visitSRA()
10370 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
10386 if (N0.getOpcode() == ISD::SHL && N1C) { in visitSRA()
10424 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C && in visitSRA()
10426 bool IsAdd = N0.getOpcode() == ISD::ADD; in visitSRA()
10428 if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 && in visitSRA()
10464 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
10465 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRA()
10474 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
10475 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
10476 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
10549 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
10573 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
10574 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
10611 if (N0.getOpcode() == ISD::SHL && in visitSRL()
10646 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
10670 if (N0.getOpcode() == ISD::SRA) in visitSRL()
10676 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
10710 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
10711 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRL()
10757 if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) in visitSRL()
10760 if (Use->getOpcode() == ISD::BRCOND || Use->getOpcode() == ISD::AND || in visitSRL()
10761 Use->getOpcode() == ISD::OR || Use->getOpcode() == ISD::XOR) in visitSRL()
10778 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
10800 return DAG.getNode(N->getOpcode(), DL, VT, N0, N1, in visitFunnelShift()
10899 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1})) in visitSHLSAT()
10906 if (N->getOpcode() == ISD::SSHLSAT && N1C && in visitSHLSAT()
10911 if (N->getOpcode() == ISD::USHLSAT && N1C && in visitSHLSAT()
10927 if (N->getOpcode() == ISD::TRUNCATE) in foldABSToABD()
10930 if (N->getOpcode() != ISD::ABS) in foldABSToABD()
10937 if (AbsOp1.getOpcode() != ISD::SUB) in foldABSToABD()
10943 unsigned Opc0 = Op0.getOpcode(); in foldABSToABD()
10947 if (Opc0 != Op1.getOpcode() || in foldABSToABD()
11000 if (N0.getOpcode() == ISD::ABS) in visitABS()
11011 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitABS()
11035 if (N0.getOpcode() == ISD::BSWAP) in visitBSWAP()
11042 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { in visitBSWAP()
11050 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) { in visitBSWAP()
11072 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
11078 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
11099 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
11187 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) { in visitCTPOP()
11192 if ((N0.getOpcode() == ISD::SRL && in visitCTPOP()
11194 (N0.getOpcode() == ISD::SHL && in visitCTPOP()
11333 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
11363 if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse()) in shouldConvertSelectOfConstantsToMath()
11499 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT || in foldBoolSelectToLogic()
11500 N->getOpcode() == ISD::VP_SELECT) && in foldBoolSelectToLogic()
11637 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { in visitSELECT()
11650 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { in visitSELECT()
11664 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { in visitSELECT()
11683 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { in visitSELECT()
11703 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
11723 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { in visitSELECT()
11780 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11781 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11782 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
11846 if (Index.getOpcode() != ISD::ADD) in refineUniformBase()
11870 if (Index.getOpcode() == ISD::ZERO_EXTEND) { in refineIndexType()
11883 if (Index.getOpcode() == ISD::SIGN_EXTEND && in refineIndexType()
11979 if (N->getOpcode() != ISD::DELETED_NODE) in visitMSTORE()
12013 if (N->getOpcode() != ISD::DELETED_NODE) in visitMSTORE()
12023 if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() && in visitMSTORE()
12306 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N2 && N1->hasOneUse() && in visitVSELECT()
12321 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
12329 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) in visitVSELECT()
12332 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) in visitVSELECT()
12378 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && in visitVSELECT()
12400 if (N1.getOpcode() == ISD::SUB && N2.getOpcode() == ISD::SUB && in visitVSELECT()
12440 if (Other && Other.getOpcode() == ISD::ADD) { in visitVSELECT()
12457 if (OpRHS.getOpcode() == CondRHS.getOpcode() && in visitVSELECT()
12458 (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12459 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
12491 if (Other && Other.getOpcode() == ISD::TRUNCATE && in visitVSELECT()
12492 Other.getOperand(0).getOpcode() == ISD::SUB && in visitVSELECT()
12496 if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND) in visitVSELECT()
12511 Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) in visitVSELECT()
12514 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12515 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
12516 if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12517 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
12526 if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && in visitVSELECT()
12539 if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && in visitVSELECT()
12568 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
12569 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
12622 if (SCC.getOpcode() == ISD::SETCC) { in visitSELECT_CC()
12644 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; in visitSETCC()
12654 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { in visitSETCC()
12681 return A.getOpcode() == ISD::AND && in visitSETCC()
12682 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) && in visitSETCC()
12686 return (B.getOpcode() == ISD::ROTL || B.getOpcode() == ISD::ROTR) && in visitSETCC()
12729 unsigned ShiftOpc = ShiftOrRotate.getOpcode(); in visitSETCC()
12824 unsigned Opcode = N->getOpcode(); in tryToFoldExtendSelectLoad()
12831 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
12852 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes && in tryToFoldExtendSelectLoad()
12870 unsigned Opcode = N->getOpcode(); in tryToFoldExtendOfConstant()
12886 if (N0->getOpcode() == ISD::SELECT) { in tryToFoldExtendOfConstant()
12964 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
12987 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
12996 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
13036 assert((N->getOpcode() == ISD::SIGN_EXTEND || in CombineExtLoad()
13037 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
13057 if (N0->getOpcode() != ISD::LOAD) in CombineExtLoad()
13069 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) in CombineExtLoad()
13073 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
13124 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); in CombineExtLoad()
13132 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
13140 if (!ISD::isBitwiseLogicOp(N0.getOpcode()) || in CombineZExtLogicopShiftLoad()
13141 N0.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
13142 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
13147 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
13148 N1.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
13149 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
13164 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) in CombineZExtLogicopShiftLoad()
13181 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, in CombineZExtLogicopShiftLoad()
13186 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, in CombineZExtLogicopShiftLoad()
13210 unsigned CastOpcode = Cast->getOpcode(); in matchVSelectOpSizesWithSetCC()
13224 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
13225 VSel.getOperand(0).getOpcode() != ISD::SETCC) in matchVSelectOpSizesWithSetCC()
13298 if (User->getOpcode() == ISD::SETCC) { in tryToFoldExtOfLoad()
13379 if (!ALoad || ALoad->getOpcode() != ISD::ATOMIC_LOAD) in tryToFoldExtOfAtomicLoad()
13406 assert((N->getOpcode() == ISD::SIGN_EXTEND || in foldExtendedSignBitTest()
13407 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
13410 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || in foldExtendedSignBitTest()
13433 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
13442 if (N0.getOpcode() != ISD::SETCC) in foldSextSetcc()
13516 if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) in foldSextSetcc()
13583 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
13588 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND()
13589 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in visitSIGN_EXTEND()
13594 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSIGN_EXTEND()
13597 if ((N00.getOpcode() == ISD::TRUNCATE || TLI.isTruncateFree(N00, ExtVT)) && in visitSIGN_EXTEND()
13604 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
13682 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && in visitSIGN_EXTEND()
13684 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
13685 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitSIGN_EXTEND()
13699 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND()
13743 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSIGN_EXTEND()
13745 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
13752 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSIGN_EXTEND()
13754 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
13793 assert((Extend->getOpcode() == ISD::ZERO_EXTEND || in widenCtPop()
13794 Extend->getOpcode() == ISD::ANY_EXTEND) && in widenCtPop()
13798 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) in widenCtPop()
13815 assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend."); in widenAbs()
13822 if (Abs.getOpcode() != ISD::ABS || !Abs.hasOneUse()) in widenAbs()
13857 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitZERO_EXTEND()
13859 if (N0.getOpcode() == ISD::ZERO_EXTEND) in visitZERO_EXTEND()
13866 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitZERO_EXTEND()
13867 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) in visitZERO_EXTEND()
13892 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
13962 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
13963 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
13964 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
13999 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && !TLI.isZExtFree(N0, VT) && in visitZERO_EXTEND()
14001 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
14002 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitZERO_EXTEND()
14010 if (N0.getOpcode() == ISD::AND) { in visitZERO_EXTEND()
14027 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
14064 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
14110 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
14115 if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) { in visitZERO_EXTEND()
14116 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
14139 return DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
14182 if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
14183 N0.getOpcode() == ISD::SIGN_EXTEND) { in visitANY_EXTEND()
14185 if (N0.getOpcode() == ISD::ZERO_EXTEND) in visitANY_EXTEND()
14187 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Flags); in visitANY_EXTEND()
14193 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitANY_EXTEND()
14194 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG || in visitANY_EXTEND()
14195 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in visitANY_EXTEND()
14196 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0)); in visitANY_EXTEND()
14200 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
14213 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
14218 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
14219 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
14220 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
14269 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && in visitANY_EXTEND()
14285 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
14336 unsigned Opcode = N->getOpcode(); in visitAssertExt()
14342 if (N0.getOpcode() == Opcode && in visitAssertExt()
14346 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
14347 N0.getOperand(0).getOpcode() == Opcode) { in visitAssertExt()
14366 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
14367 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
14397 switch (N0.getOpcode()) { in visitAssertAlign()
14412 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); in visitAssertAlign()
14425 unsigned Opc = N->getOpcode(); in reduceLoadWidth()
14503 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
14551 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
14586 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in reduceLoadWidth()
14691 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
14700 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
14712 if (ISD::isExtVecInRegOpcode(N0.getOpcode())) { in visitSIGN_EXTEND_INREG()
14717 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in visitSIGN_EXTEND_INREG()
14729 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
14753 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
14838 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
14848 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && in visitSIGN_EXTEND_INREG()
14849 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitSIGN_EXTEND_INREG()
14870 unsigned InregOpcode = N->getOpcode(); in foldExtendVectorInregToExtendOfSubvector()
14884 if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) in foldExtendVectorInregToExtendOfSubvector()
14907 return N->getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG in visitEXTEND_VECTOR_INREG()
14937 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
14945 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
14946 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
14947 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
14950 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0)); in visitTRUNCATE()
14961 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitTRUNCATE()
14973 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) in visitTRUNCATE()
14986 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
15010 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { in visitTRUNCATE()
15022 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in visitTRUNCATE()
15046 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && in visitTRUNCATE()
15061 if (N0.getOpcode() == ISD::SPLAT_VECTOR && in visitTRUNCATE()
15074 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
15075 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
15101 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
15121 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
15166 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { in visitTRUNCATE()
15186 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
15188 if (N00.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
15189 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
15190 N00.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
15205 switch (N0.getOpcode()) { in visitTRUNCATE()
15218 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { in visitTRUNCATE()
15221 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); in visitTRUNCATE()
15232 if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) || in visitTRUNCATE()
15233 TLI.isOperationLegal(N0.getOpcode(), VT)) && in visitTRUNCATE()
15238 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2)); in visitTRUNCATE()
15246 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitTRUNCATE()
15249 hasOperation(N0.getOpcode(), VT)) { in visitTRUNCATE()
15261 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
15269 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
15322 switch (N0.getOpcode()) { in foldBitcastedFPLogic()
15346 if (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).getValueType() == VT) in foldBitcastedFPLogic()
15363 if (N0.getOpcode() == ISD::OR) in foldBitcastedFPLogic()
15388 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() && in visitBITCAST()
15410 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
15415 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() && in visitBITCAST()
15418 return (V.getOpcode() == ISD::BITCAST && in visitBITCAST()
15424 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, in visitBITCAST()
15469 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
15470 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
15482 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
15486 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
15501 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
15504 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
15520 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitBITCAST()
15584 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
15593 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
15601 if (Op.getOpcode() == ISD::BITCAST && in visitBITCAST()
15647 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) in visitFREEZE()
15663 N0.getOpcode() == ISD::SELECT_CC || in visitFREEZE()
15664 N0.getOpcode() == ISD::SETCC || in visitFREEZE()
15665 N0.getOpcode() == ISD::BUILD_VECTOR || in visitFREEZE()
15666 N0.getOpcode() == ISD::BUILD_PAIR || in visitFREEZE()
15667 N0.getOpcode() == ISD::VECTOR_SHUFFLE || in visitFREEZE()
15668 N0.getOpcode() == ISD::CONCAT_VECTORS; in visitFREEZE()
15676 if (N0.getOpcode() == ISD::BUILD_VECTOR) { in visitFREEZE()
15724 if (MaybePoisonOperand.getOpcode() == ISD::UNDEF) in visitFREEZE()
15730 if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE && in visitFREEZE()
15740 if (N->getOpcode() == ISD::DELETED_NODE) in visitFREEZE()
15752 if (Op.getOpcode() == ISD::UNDEF) in visitFREEZE()
15763 R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops); in visitFREEZE()
15850 assert(N.getOpcode() == ISD::FMUL); in isContractableFMUL()
15968 return FMA.getOpcode() == ISD::DELETED_NODE ? SDValue(N, 0) : FMA; in visitFADDForFMACombine()
16045 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
16063 if (N12.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
16080 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
16435 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
16441 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine()
16467 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
16490 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
16526 if (Fused.getOpcode() != ISD::DELETED_NODE) in visitVP_FADD()
16544 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFADD()
16582 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
16608 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
16612 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
16623 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
16633 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
16647 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
16656 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
16670 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && in visitFADD()
16679 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
16690 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
16702 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
16719 if (Fused.getOpcode() != ISD::DELETED_NODE) in visitFADD()
16764 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFSUB()
16814 N1.getOpcode() == ISD::FADD) { in visitFSUB()
16858 if (ConstOpIdx == 1 && N->getOpcode() == ISD::FDIV) in combineFMulOrFDivWithIntPow2()
16863 if (Pow2Op.getOpcode() != ISD::UINT_TO_FP && in combineFMulOrFDivWithIntPow2()
16864 (Pow2Op.getOpcode() != ISD::SINT_TO_FP || in combineFMulOrFDivWithIntPow2()
16889 N->getOpcode() == ISD::FMUL ? CurExp : (CurExp - MaxExpChange); in combineFMulOrFDivWithIntPow2()
16892 N->getOpcode() == ISD::FDIV ? CurExp : (CurExp + MaxExpChange); in combineFMulOrFDivWithIntPow2()
16937 DAG.getNode(N->getOpcode() == ISD::FMUL ? ISD::ADD : ISD::SUB, DL, in combineFMulOrFDivWithIntPow2()
16953 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFMUL()
16976 N0.getOpcode() == ISD::FMUL) { in visitFMUL()
16990 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && in visitFMUL()
17034 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && in visitFMUL()
17037 if (Select.getOpcode() != ISD::SELECT) in visitFMUL()
17045 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && in visitFMUL()
17272 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { in combineRepeatedFPDivisors()
17274 if (U->getOperand(1).getOpcode() == ISD::FSQRT && in combineRepeatedFPDivisors()
17321 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFDIV()
17364 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
17367 } else if (N1.getOpcode() == ISD::FP_EXTEND && in visitFDIV()
17368 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
17375 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
17376 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
17383 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
17387 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
17390 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
17400 if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) in visitFDIV()
17437 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) in visitFDIV()
17470 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFREM()
17547 if (N1.getOpcode() != ISD::FP_EXTEND && in CanCombineFCOPYSIGN_EXTEND_ROUND()
17548 N1.getOpcode() != ISD::FP_ROUND) in CanCombineFCOPYSIGN_EXTEND_ROUND()
17582 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
17583 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
17587 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
17591 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
17706 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
17710 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && in foldFPToIntToFP()
17744 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
17754 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
17755 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && in visitSINT_TO_FP()
17795 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
17813 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
17818 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
17819 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; in FoldIntToFPToInt()
17890 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0); in visitXRINT()
17906 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
17910 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
17946 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitFP_ROUND()
17972 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
17980 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
17986 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
18041 switch (N0.getOpcode()) { in visitFTRUNC()
18092 if (N0.getOpcode() == ISD::FSUB && in visitFNEG()
18110 unsigned Opc = N->getOpcode(); in visitFMinMax()
18122 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitFMinMax()
18172 if (N0.getOpcode() == ISD::FABS) in visitFABS()
18177 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
18193 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { in visitBRCOND()
18208 if (N1->getOpcode() == ISD::SETCC && N1.hasOneUse()) { in visitBRCOND()
18228 if (S0->getOpcode() == ISD::FREEZE && S0.hasOneUse() && S1C) { in visitBRCOND()
18234 if (S1->getOpcode() == ISD::FREEZE && S1.hasOneUse() && S0C) { in visitBRCOND()
18255 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
18276 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
18277 (N.getOpcode() == ISD::TRUNCATE && in rebuildSetCC()
18279 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
18281 if (N.getOpcode() == ISD::TRUNCATE) in rebuildSetCC()
18304 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { in rebuildSetCC()
18307 if (AndOp1.getOpcode() == ISD::Constant) { in rebuildSetCC()
18323 if (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
18330 while (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
18343 if (N.getOpcode() != ISD::XOR) in rebuildSetCC()
18349 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
18352 if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && in rebuildSetCC()
18391 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
18461 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
18536 if (Use.getUser()->getOpcode() != ISD::ADD && in CombineToPreIndexedLoadStore()
18537 Use.getUser()->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
18633 int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; in CombineToPreIndexedLoadStore()
18634 int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; in CombineToPreIndexedLoadStore()
18672 (PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) in shouldCombineToPostInc()
18706 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { in shouldCombineToPostInc()
18814 assert((Inc.getOpcode() != ISD::TargetConstant || in SplitIndexingFromLoad()
18817 if (Inc.getOpcode() == ISD::TargetConstant) { in SplitIndexingFromLoad()
18887 if (Chain.getOpcode() == ISD::CALLSEQ_START) in getUniqueStoreFeeding()
18892 if (Chain.getOpcode() == ISD::TokenFactor) { in getUniqueStoreFeeding()
19445 if (Use->getOpcode() != ISD::BITCAST) in canMergeExpensiveCrossRegisterBankCopy()
19663 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
19671 if (User->getOpcode() != ISD::TRUNCATE) in SliceUpLoad()
19714 if (SliceInst.getOpcode() != ISD::LOAD) in SliceUpLoad()
19716 assert(SliceInst->getOpcode() == ISD::LOAD && in SliceUpLoad()
19736 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
19785 else if (Chain->getOpcode() == ISD::TokenFactor && in CheckForMaskedLoad()
19894 unsigned Opc = Value.getOpcode(); in ReduceLoadOpStoreWidth()
19924 if (Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
20095 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. in isMulAddWithConstProfitable()
20131 if (OtherOp->getOpcode() == ISD::ADD && in isMulAddWithConstProfitable()
20273 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
20274 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
20280 Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in mergeStoresOfConstantsOrVecElts()
20470 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
20471 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
20575 if (N->getOpcode() == ISD::TokenFactor) { in checkMergeStoreCandidatesForDependencies()
21272 if (Value.getOpcode() == ISD::TargetConstantFP) in replaceStoreOfFPConstant()
21358 if (Value.getOpcode() != ISD::INSERT_VECTOR_ELT || !Value.hasOneUse()) in replaceStoreOfInsertLoad()
21430 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
21495 if ((Value.getOpcode() == ISD::ZERO_EXTEND || in visitSTORE()
21496 Value.getOpcode() == ISD::SIGN_EXTEND || in visitSTORE()
21497 Value.getOpcode() == ISD::ANY_EXTEND) && in visitSTORE()
21515 if (N->getOpcode() != ISD::DELETED_NODE) in visitSTORE()
21613 if ((Value.getOpcode() == ISD::FP_ROUND || in visitSTORE()
21614 Value.getOpcode() == ISD::TRUNCATE) && in visitSTORE()
21634 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N)) in visitSTORE()
21673 switch (Chain.getOpcode()) { in visitLIFETIME_END()
21753 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) in splitMergedValStore()
21760 if (Op1.getOpcode() != ISD::SHL) { in splitMergedValStore()
21762 if (Op1.getOpcode() != ISD::SHL) in splitMergedValStore()
21778 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
21781 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
21788 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
21791 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
21828 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in mergeEltWithShuffle()
21856 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in mergeEltWithShuffle()
21893 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in mergeInsertEltWithShuffle()
21923 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in combineInsertEltToShuffle()
21927 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || in combineInsertEltToShuffle()
22004 if (Scalar.getOpcode() == ISD::ZERO_EXTEND || in combineInsertEltToLoad()
22005 Scalar.getOpcode() == ISD::SIGN_EXTEND || in combineInsertEltToLoad()
22006 Scalar.getOpcode() == ISD::ANY_EXTEND) { in combineInsertEltToLoad()
22007 Extend = Scalar.getOpcode(); in combineInsertEltToLoad()
22017 if (Vec.getOpcode() != Extend) in combineInsertEltToLoad()
22087 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
22110 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
22123 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
22187 if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
22194 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
22200 if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse()) in visitINSERT_VECTOR_ELT()
22217 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
22362 if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || in scalarizeExtractedBinop()
22385 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
22468 switch (User->getOpcode()) { in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22497 if (User->getOpcode() != ISD::BUILD_VECTOR) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22566 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
22573 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22598 if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || in visitEXTRACT_VECTOR_ELT()
22599 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
22601 assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || in visitEXTRACT_VECTOR_ELT()
22605 VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; in visitEXTRACT_VECTOR_ELT()
22648 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && in visitEXTRACT_VECTOR_ELT()
22660 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22687 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
22705 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22730 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
22743 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
22751 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
22769 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
22804 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
22831 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
22843 } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && in visitEXTRACT_VECTOR_ELT()
22908 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
22909 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
22965 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
22966 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
23004 assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecTruncToBitCast()
23029 if (Op.getOpcode() == ISD::BITCAST) in reduceBuildVecTruncToBitCast()
23041 if (In.getOpcode() != ISD::TRUNCATE) in reduceBuildVecTruncToBitCast()
23046 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
23226 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecToShuffleWithZero()
23253 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
23254 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffleWithZero()
23358 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
23533 bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
23542 bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
23582 unsigned Opc = Op.getOpcode(); in convertBuildVecZextToZext()
23585 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && in convertBuildVecZextToZext()
23674 if (Op.getOpcode() != ISD::ZERO_EXTEND) in convertBuildVecZextToBuildVecWithZeros()
23783 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
23851 if (ISD::BITCAST == Op.getOpcode() && in combineConcatVectorOfScalars()
23854 else if (ISD::UNDEF == Op.getOpcode()) in combineConcatVectorOfScalars()
23905 if (Op.getOpcode() != ISD::CONCAT_VECTORS) in combineConcatVectorOfConcatVectors()
23957 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
24009 unsigned CastOpcode = N->getOperand(0).getOpcode(); in combineConcatVectorOfCasts()
24034 if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || in combineConcatVectorOfCasts()
24197 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() && in visitCONCAT_VECTORS()
24209 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
24221 if (Scalar->getOpcode() == ISD::TRUNCATE && in visitCONCAT_VECTORS()
24253 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); in visitCONCAT_VECTORS()
24265 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
24277 if (ISD::UNDEF == Op.getOpcode()) in visitCONCAT_VECTORS()
24280 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
24336 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
24368 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
24373 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
24387 unsigned BinOpcode = BinOp.getOpcode(); in narrowInsertExtractVectorBinOp()
24436 unsigned BOpcode = BinOp.getOpcode(); in narrowExtractedVectorBinOp()
24518 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) in narrowExtractedVectorBinOp()
24620 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && in foldExtractSubvectorFromShuffleVector()
24779 if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { in visitEXTRACT_SUBVECTOR()
24789 if (V.getOpcode() == ISD::SPLAT_VECTOR) in visitEXTRACT_SUBVECTOR()
24797 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
24813 if (V.getOpcode() == ISD::BITCAST && in visitEXTRACT_SUBVECTOR()
24862 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
24904 if (V.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_SUBVECTOR()
24936 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
24978 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
24979 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
25143 if (S.getOpcode() == ISD::BUILD_VECTOR) { in combineShuffleOfScalars()
25145 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
25398 unsigned Opcode = N0.getOpcode(); in combineTruncationShuffle()
25555 if (Op0.getOpcode() != ISD::BITCAST) in combineShuffleOfBitcast()
25559 (!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST || in combineShuffleOfBitcast()
25699 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
25804 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) { in visitVECTOR_SHUFFLE()
25814 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags()); in visitVECTOR_SHUFFLE()
25824 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) in visitVECTOR_SHUFFLE()
25827 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT) in visitVECTOR_SHUFFLE()
25834 if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() && in visitVECTOR_SHUFFLE()
25836 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR || in visitVECTOR_SHUFFLE()
25837 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) { in visitVECTOR_SHUFFLE()
25854 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
25861 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
25916 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
25919 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
25928 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && in visitVECTOR_SHUFFLE()
25957 assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors"); in visitVECTOR_SHUFFLE()
26002 if (N1.getOpcode() == ISD::CONCAT_VECTORS) in visitVECTOR_SHUFFLE()
26005 if (N0.getOpcode() == ISD::CONCAT_VECTORS) { in visitVECTOR_SHUFFLE()
26076 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitVECTOR_SHUFFLE()
26081 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
26255 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
26256 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
26273 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
26274 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
26288 if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
26315 unsigned SrcOpcode = N0.getOpcode(); in visitVECTOR_SHUFFLE()
26318 (SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { in visitVECTOR_SHUFFLE()
26329 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
26330 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
26331 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
26332 Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { in visitVECTOR_SHUFFLE()
26414 unsigned Opcode = Scalar.getOpcode(); in visitSCALAR_TO_VECTOR()
26431 if (C && EE.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitSCALAR_TO_VECTOR()
26510 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26532 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && N1.getOperand(0) == N0 && in visitINSERT_SUBVECTOR()
26538 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) in visitINSERT_SUBVECTOR()
26546 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && in visitINSERT_SUBVECTOR()
26547 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26560 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
26577 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26586 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26595 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && in visitINSERT_SUBVECTOR()
26596 N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
26633 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
26648 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
26669 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
26676 auto Op = N->getOpcode(); in visitFP16_TO_FP()
26683 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { in visitFP16_TO_FP()
26693 SDValue Folded = DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), in visitFP16_TO_FP()
26702 if (N0->getOpcode() == ISD::BF16_TO_FP) in visitFP_TO_BF16()
26716 unsigned Opcode = N->getOpcode(); in visitVECREDUCE()
26742 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitVECREDUCE()
26769 if (N->getOpcode() == ISD::VP_GATHER) in visitVPOp()
26773 if (N->getOpcode() == ISD::VP_SCATTER) in visitVPOp()
26777 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD) in visitVPOp()
26781 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE) in visitVPOp()
26789 if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode())) in visitVPOp()
26791 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) in visitVPOp()
26797 switch (N->getOpcode()) { in visitVPOp()
26815 if (ISD::isVPBinaryOp(N->getOpcode())) in visitVPOp()
26827 if (ISD::isVPReduction(N->getOpcode())) in visitVPOp()
26929 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); in XformToShuffleWithZero()
26941 if (RHS.getOpcode() != ISD::BUILD_VECTOR) in XformToShuffleWithZero()
27019 unsigned Opcode = N->getOpcode(); in scalarizeBinOpOfSplats()
27032 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && in scalarizeBinOpOfSplats()
27033 N1.getOpcode() == ISD::SPLAT_VECTOR; in scalarizeBinOpOfSplats()
27048 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && in scalarizeBinOpOfSplats()
27067 unsigned Opcode = N->getOpcode(); in SimplifyVCastOp()
27076 (N0.getOpcode() == ISD::SPLAT_VECTOR || in SimplifyVCastOp()
27102 unsigned Opcode = N->getOpcode(); in SimplifyVBinOp()
27132 Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
27141 Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
27154 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && in SimplifyVBinOp()
27155 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && in SimplifyVBinOp()
27175 return Concat.getOpcode() == ISD::CONCAT_VECTORS && in SimplifyVBinOp()
27212 assert(N0.getOpcode() == ISD::SETCC && in SimplifySelect()
27224 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
27252 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
27259 if (TheSelect->getOpcode() == ISD::SELECT_CC) { in SimplifySelectOps()
27266 if (Cmp.getOpcode() == ISD::SETCC) { in SimplifySelectOps()
27286 if (LHS.getOpcode() != RHS.getOpcode() || in SimplifySelectOps()
27294 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
27323 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
27324 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
27325 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), in SimplifySelectOps()
27352 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
27513 unsigned BinOpc = N1.getOpcode(); in foldSelectOfBinops()
27514 if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc) || in foldSelectOfBinops()
27565 bool IsFabs = N->getOpcode() == ISD::FABS; in foldSignChangeInBitcast()
27568 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) in foldSignChangeInBitcast()
27696 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
27783 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
27784 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in SimplifySelectCC()
27790 if ((Count.getOpcode() == ISD::CTLZ || in SimplifySelectCC()
27791 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && in SimplifySelectCC()
27929 switch (V.getOpcode()) { in takeInexpensiveLog2()
27963 if (Op.getOpcode() == ISD::SPLAT_VECTOR) in takeInexpensiveLog2()
27990 if (Op.getOpcode() == ISD::SHL) { in takeInexpensiveLog2()
28001 if ((Op.getOpcode() == ISD::SELECT || Op.getOpcode() == ISD::VSELECT) && in takeInexpensiveLog2()
28012 if ((Op.getOpcode() == ISD::UMIN || Op.getOpcode() == ISD::UMAX) && in takeInexpensiveLog2()
28022 return DAG.getNode(Op.getOpcode(), DL, VT, LogX, LogY); in takeInexpensiveLog2()
28424 switch (C.getOpcode()) { in GatherAllAliases()
28487 if (Chain.getOpcode() == ISD::TokenFactor) { in GatherAllAliases()