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Searched refs:getDesc (Results 1 – 25 of 193) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp91 User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm(); in hasSameEEW()
93 Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm(); in hasSameEEW()
151 MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc())); in tryToReduceVL()
165 !RISCVII::hasVLOp(Src->getDesc().TSFlags) || in tryToReduceVL()
166 !RISCVII::hasSEWOp(Src->getDesc().TSFlags)) in tryToReduceVL()
179 Src->getOperand(RISCVII::getVLOpNum(Src->getDesc())); in tryToReduceVL()
214 if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) || in convertToVLMAX()
215 !RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in convertToVLMAX()
218 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX()
221 unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in convertToVLMAX()
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H A DRISCVSelectionDAGInfo.h38 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasPassthruOpMask; in hasPassthruOp()
42 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasMaskOpMask; in hasMaskOp()
H A DRISCVVMV0Elimination.cpp102 if (any_of(MI.getDesc().operands(), isVMV0)) in runOnMachineFunction()
119 assert(count_if(MI.getDesc().operands(), isVMV0) < 2 && in runOnMachineFunction()
122 for (auto [OpNo, MCOI] : enumerate(MI.getDesc().operands())) { in runOnMachineFunction()
H A DRISCVVLOptimizer.cpp144 RISCVVType::VLMUL MIVLMUL = RISCVII::getLMul(MI.getDesc().TSFlags); in getEMULEqualsEEWDivSEWTimesLMUL()
147 MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in getEMULEqualsEEWDivSEWTimesLMUL()
173 MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in getIntegerExtensionOperandEEW()
192 const MCInstrDesc &Desc = MI.getDesc(); in isMaskOperand()
206 MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in getOperandLog2EEW()
208 const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MI.getDesc()); in getOperandLog2EEW()
209 const bool IsTied = RISCVII::isTiedPseudo(MI.getDesc().TSFlags); in getOperandLog2EEW()
1236 const MCInstrDesc &Desc = MI.getDesc(); in isCandidate()
1286 const MCInstrDesc &Desc = UserMI.getDesc(); in getMinimumVLForUser()
1309 RISCVII::isFirstDefTiedToFirstUse(UserMI.getDesc())); in getMinimumVLForUser()
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H A DRISCVInsertReadWriteCSR.cpp99 int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc()); in INITIALIZE_PASS()
146 int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc()); in emitWriteRoundingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h428 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
436 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
460 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
468 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
476 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
484 return MI.getDesc().TSFlags & SIInstrFlags::SOPK; in isSOPK()
492 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
500 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked; in isPacked()
508 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
516 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
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H A DSIPostRABundler.cpp118 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
124 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
128 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
H A DGCNVOPDUtils.cpp86 AMDGPU::getVOPDInstInfo(FirstMI.getDesc(), SecondMI.getDesc()); in checkVOPDRegConstraints()
110 if (MI.getDesc().hasImplicitUseOfPhysReg(AMDGPU::VCC)) in checkVOPDRegConstraints()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
255 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in HexagonMCInstrInfo
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
435 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getCVIResources()
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H A DHexagonShuffler.cpp130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
131 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
198 MCInst const &Inst = ISJ.getDesc(); in restrictSlot1AOK()
230 MCInst const &Inst = ISJ.getDesc(); in restrictNoSlot1Store()
231 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
365 MCInst const &ID = ISJ->getDesc(); in restrictStoreLoadOrder()
372 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
405 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
456 MCInst const &ID = ISJ->getDesc(); in GetPacketSummary()
501 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
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H A DHexagonMCShuffler.cpp41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
85 MCInst const &MI = I.getDesc(); in copyTo()
H A DHexagonMCChecker.cpp93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
425 bool Branch = HexagonMCInstrInfo::getDesc(MCII, ConsumerInst).isBranch(); in checkNewValues()
473 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst); in checkNewValues()
530 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
547 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
564 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
590 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SuppressAPXForReloc.cpp105 int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) + in handleInstructionWithEGPR()
106 X86II::getOperandBias(MI.getDesc()); in handleInstructionWithEGPR()
175 int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) + in handleNDDOrNFInstructions()
176 X86II::getOperandBias(MI.getDesc()); in handleNDDOrNFInstructions()
183 int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) + in handleNDDOrNFInstructions()
184 X86II::getOperandBias(MI.getDesc()); in handleNDDOrNFInstructions()
206 int MemRefBegin = X86II::getMemoryOperandNo(MI.getDesc().TSFlags); in handleNDDOrNFInstructions()
H A DX86DiscriminateMemOps.cpp113 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
129 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0) in runOnMachineFunction()
131 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp38 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
65 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
66 J->getDesc().isIndirectBranch()) { in analyzeBranch()
82 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
90 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
96 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
102 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && in analyzeBranch()
103 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
121 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
122 !I->getDesc().isConditionalBranch()) in removeBranch()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSDNodeInfo.h95 const SDNodeDesc &getDesc(unsigned Opcode) const { in getDesc() function
102 const SDNodeDesc &Desc = getDesc(Opcode); in getConstraints()
109 return Names[getDesc(Opcode).NameOffset]; in getName()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp95 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
120 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
187 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
223 !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() && in computeOperandLatency()
308 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
H A DExecutionDomainFix.cpp237 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
260 e = mi->getDesc().getNumOperands(); in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
291 e = mi->getDesc().getNumOperands(); in visitSoftInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp244 const MCInstrDesc &Desc = MI.getDesc(); in getInstSizeInBytes()
280 assert(MI.getDesc().isBranch() && "Unexpected opcode!"); in getBranchDestBlock()
288 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
318 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
319 J->getDesc().isIndirectBranch()) { in analyzeBranch()
335 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
341 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
347 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && in analyzeBranch()
348 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
554 if (!I->getDesc().isBranch()) in removeBranch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp29 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
50 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
53 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
110 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset()
H A DARMBaseRegisterInfo.cpp561 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
753 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
869 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
870 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 || in eliminateFrameIndex()
871 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 || in eliminateFrameIndex()
872 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 || in eliminateFrameIndex()
873 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == in eliminateFrameIndex()
883 const MCInstrDesc &MCID = MI.getDesc(); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DStatistic.cpp150 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in sort()
197 MaxDebugTypeLen, Stat->getDebugType(), Stat->getDesc()); in PrintStatistics()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp74 const InstrDesc &D = IS->getDesc(); in issueInstructionImpl()
200 uint64_t BusyResourceMask = Resources->checkAvailability(IS.getDesc()); in select()
254 if (Resources->checkAvailability(IS.getDesc())) in analyzeDataDependencies()
292 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in mustIssueImmediately()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1671 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1761 if (!MI.getDesc().isPredicable()) in isPredicable()
1821 if (MI.getDesc().isTerminator() || MI.isPosition()) in isSchedulingBoundary()
2126 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
2135 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() && in isComplex()
2136 !MI.getDesc().mayStore() && in isComplex()
2137 MI.getDesc().getOpcode() != Hexagon::S2_allocframe && in isComplex()
2138 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe && in isComplex()
2150 const uint64_t F = MI.getDesc().TSFlags; in isConstExtended()
2215 if (!ProdMI.getDesc().getNumDefs()) in isDependent()
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