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Searched refs:getDesc (Results 1 – 25 of 181) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h409 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
417 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
441 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
449 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
457 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
465 return MI.getDesc().TSFlags & SIInstrFlags::SOPK; in isSOPK()
473 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
481 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked; in isPacked()
489 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
497 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
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H A DGCNVOPDUtils.cpp78 AMDGPU::getVOPDInstInfo(FirstMI.getDesc(), SecondMI.getDesc()); in checkVOPDRegConstraints()
98 if (MI.getDesc().hasImplicitUseOfPhysReg(AMDGPU::VCC)) in checkVOPDRegConstraints()
H A DSIPostRABundler.cpp110 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
116 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
120 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
H A DGCNCreateVOPD.cpp89 AMDGPU::getVOPDInstInfo(FirstMI->getDesc(), SecondMI->getDesc()); in doReplace()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
255 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in HexagonMCInstrInfo
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
435 int SchedClass = HexagonMCInstrInfo::getDesc(MCI in getCVIResources()
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H A DHexagonShuffler.cpp131 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
132 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
199 MCInst const &Inst = ISJ.getDesc(); in restrictSlot1AOK()
231 MCInst const &Inst = ISJ.getDesc(); in restrictNoSlot1Store()
232 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
366 MCInst const &ID = ISJ->getDesc(); in restrictStoreLoadOrder()
373 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
406 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
457 MCInst const &ID = ISJ->getDesc(); in GetPacketSummary()
502 if (HexagonMCInstrInfo::getDesc(MCI in GetPacketSummary()
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H A DHexagonMCShuffler.cpp41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
85 MCInst const &MI = I.getDesc(); in copyTo()
H A DHexagonMCChecker.cpp93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
425 bool Branch = HexagonMCInstrInfo::getDesc(MCII, ConsumerInst).isBranch(); in checkNewValues()
473 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst); in checkNewValues()
530 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
547 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
564 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
590 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp229 return MI.getDesc().getSize(); in getInstSizeInBytes()
249 assert(MI.getDesc().isBranch() && "Unexpected opcode!"); in getBranchDestBlock()
257 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
287 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
288 J->getDesc().isIndirectBranch()) { in analyzeBranch()
304 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
310 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
316 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && in analyzeBranch()
317 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
358 if (!I->getDesc().isBranch()) in removeBranch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp38 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
65 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
66 J->getDesc().isIndirectBranch()) { in analyzeBranch()
82 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
90 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
96 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
102 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && in analyzeBranch()
103 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
121 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
122 !I->getDesc().isConditionalBranch()) in removeBranch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp81 if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) || in convertToVLMAX()
82 !RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in convertToVLMAX()
84 MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc())); in convertToVLMAX()
107 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX()
110 unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in convertToVLMAX()
H A DRISCVInsertReadWriteCSR.cpp99 int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc()); in INITIALIZE_PASS()
146 int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc()); in emitWriteRoundingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp98 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
123 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
190 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
226 !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() && in computeOperandLatency()
311 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
H A DExecutionDomainFix.cpp237 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
260 e = mi->getDesc().getNumOperands(); in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
291 e = mi->getDesc().getNumOperands(); in visitSoftInstr()
H A DPeepholeOptimizer.cpp932 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1232 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1377 const MCInstrDesc &MCID = MI.getDesc(); in isLoadFoldable()
1396 const MCInstrDesc &MCID = MI.getDesc(); in isMoveImmediate()
1419 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) { in foldImmediate()
1583 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1828 const MCInstrDesc &MIDesc = MI->getDesc(); in runOnMachineFunction()
1911 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2127 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2128 Def->getDesc().isVariadic())) || in getNextSourceImpl()
H A DCriticalAntiDepBreaker.cpp188 if (i < MI.getDesc().getNumOperands()) in PrescanInstruction()
189 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
315 if (i < MI.getDesc().getNumOperands()) in ScanInstruction()
316 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DiscriminateMemOps.cpp116 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
132 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0) in runOnMachineFunction()
134 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp31 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
52 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
55 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset()
H A DARMBaseRegisterInfo.cpp532 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
724 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
840 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
841 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 || in eliminateFrameIndex()
842 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 || in eliminateFrameIndex()
843 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 || in eliminateFrameIndex()
844 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == in eliminateFrameIndex()
854 const MCInstrDesc &MCID = MI.getDesc(); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DStatistic.cpp150 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in sort()
197 MaxDebugTypeLen, Stat->getDebugType(), Stat->getDesc()); in PrintStatistics()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp74 const InstrDesc &D = IS->getDesc(); in issueInstructionImpl()
199 uint64_t BusyResourceMask = Resources->checkAvailability(IS.getDesc()); in select()
253 if (Resources->checkAvailability(IS.getDesc())) in analyzeDataDependencies()
291 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in mustIssueImmediately()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1668 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1758 if (!MI.getDesc().isPredicable()) in isPredicable()
1818 if (MI.getDesc().isTerminator() || MI.isPosition()) in isSchedulingBoundary()
2123 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
2132 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() && in isComplex()
2133 !MI.getDesc().mayStore() && in isComplex()
2134 MI.getDesc().getOpcode() != Hexagon::S2_allocframe && in isComplex()
2135 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe && in isComplex()
2147 const uint64_t F = MI.getDesc().TSFlags; in isConstExtended()
2212 if (!ProdMI.getDesc().getNumDefs()) in isDependent()
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H A DHexagonOptAddrMode.cpp131 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
198 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
378 const MCInstrDesc &MID = MI->getDesc(); in getBaseOpPosition()
400 const MCInstrDesc &MID = MI->getDesc(); in getOffsetOpPosition()
427 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
522 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
704 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
751 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp581 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0; in SafeInForbiddenSlot()
628 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0; in HasForbiddenSlot()
670 return MI.getDesc().getSize(); in getInstSizeInBytes()
741 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
749 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands(); in genInstrWithNewOpc()
758 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
777 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()

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