1668   const uint64_t F = MI.getDesc().TSFlags;  in isPredicated()
1758   if (!MI.getDesc().isPredicable())  in isPredicable()
1818   if (MI.getDesc().isTerminator() || MI.isPosition())  in isSchedulingBoundary()
2123   const uint64_t F = MI.getDesc().TSFlags;  in isAccumulator()
2132   return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&  in isComplex()
2133          !MI.getDesc().mayStore() &&  in isComplex()
2134          MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&  in isComplex()
2135          MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&  in isComplex()
2147   const uint64_t F = MI.getDesc().TSFlags;  in isConstExtended()
2212   if (!ProdMI.getDesc().getNumDefs())  in isDependent()
2287   const MCInstrDesc &MID = MI.getDesc();  in isExtendable()
2310   const uint64_t F = MI.getDesc().TSFlags;  in isExtended()
2473   const uint64_t F = MI.getDesc().TSFlags;  in isNewValue()
2495   const uint64_t F = MI.getDesc().TSFlags;  in isNewValueStore()
2507   const uint64_t F = MI.getDesc().TSFlags;  in isOperandExtended()
2513   const uint64_t F = MI.getDesc().TSFlags;  in isPredicatedNew()
2525   const uint64_t F = MI.getDesc().TSFlags;  in isPredicatedTrue()
2641   const uint64_t F = MI.getDesc().TSFlags;  in isSolo()
2667   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC1()
2672   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC2()
2677   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC2Early()
2682   unsigned SchedClass = MI.getDesc().getSchedClass();  in isTC4x()
3131   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {  in hasNonExtEquivalent()
3177   const uint64_t F = MI.getDesc().TSFlags;  in mayBeCurLoad()
3187   const uint64_t F = MI.getDesc().TSFlags;  in mayBeNewStore()
3282   const uint64_t F = MI.getDesc().TSFlags;  in getAddrMode()
3419   const uint64_t F = MI.getDesc().TSFlags;  in getCExtOpNum()
4316   return ItinData->getStageLatency(MI.getDesc().getSchedClass());  in getInstrTimingClassLatency()
4392   const uint64_t F = MI.getDesc().TSFlags;  in getMaxValue()
4423   const uint64_t F = MI.getDesc().TSFlags;  in isAddrModeWithOffset()
4446   const uint64_t F = MI.getDesc().TSFlags;  in isRestrictNoSlot1Store()
4491   const uint64_t F = MI.getDesc().TSFlags;  in getMemAccessSize()
4512   const uint64_t F = MI.getDesc().TSFlags;  in getMinValue()
4532   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {  in getNonExtOpcode()
4585   unsigned Size = MI.getDesc().getSize();  in getSize()
4616   const uint64_t F = MI.getDesc().TSFlags;  in getType()
4622   const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());  in getUnits()
4689                       << "  Class: " << NewMI->getDesc().getSchedClass());  in genAllInsnTimingClasses()