/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600MachineScheduler.cpp | 363 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot() 366 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); in AssignSlot() 369 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); in AssignSlot() 372 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); in AssignSlot()
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H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 93 if (MRI->constrainRegClass(DstReg, ST->getBoolRC())) in markAsLaneMask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64MIPeepholeOpt.cpp | 544 MRI->constrainRegClass(SrcReg, FirstInstrOperandRC); in splitTwoPartImm() 545 MRI->constrainRegClass(NewTmpReg, SecondInstrOperandRC); in splitTwoPartImm() 547 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in splitTwoPartImm() 668 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDef)); in visitINSvi64lane() 687 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDef)); in visitFMOVDr() 717 MRI->constrainRegClass(SrcReg, MRI->getRegClass(InputReg)); in visitCopy()
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H A D | AArch64ConditionalCompares.cpp | 641 MRI->constrainRegClass(HeadCond[2].getReg(), in convert() 688 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert() 691 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
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H A D | AArch64InstrInfo.cpp | 792 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect() 798 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect() 838 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect() 842 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect() 846 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect() 849 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect() 877 MRI.constrainRegClass(TrueReg, RC); in insertSelect() 878 MRI.constrainRegClass(FalseReg, RC); in insertSelect() 1268 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass() 3424 MRI.constrainRegClass(AM.BaseReg, &AArch64::GPR64spRegClass); in emitLdStWithAddr() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 70 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() function 85 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( in constrainRegClass() function in MachineRegisterInfo 89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass() 110 if (!::constrainRegClass( in constrainRegAttrs()
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H A D | OptimizePHIs.cpp | 179 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
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H A D | UnreachableBlockElim.cpp | 178 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
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H A D | MachineLoopUtils.cpp | 67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg())); in PeelSingleBlockLoop()
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H A D | TargetInstrInfo.cpp | 1106 MRI.constrainRegClass(RegA, RC); in reassociateOps() 1108 MRI.constrainRegClass(RegB, RC); in reassociateOps() 1110 MRI.constrainRegClass(RegX, RC); in reassociateOps() 1112 MRI.constrainRegClass(RegY, RC); in reassociateOps() 1114 MRI.constrainRegClass(RegC, RC); in reassociateOps()
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H A D | MachineSSAUpdater.cpp | 245 if (UseRC && !MRI->constrainRegClass(NewVR, UseRC)) { in RewriteUse()
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H A D | TailDuplicator.cpp | 260 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate() 445 : MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
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H A D | ModuloSchedule.cpp | 1190 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr() 1245 MRI.constrainRegClass(MI.getOperand(1).getReg(), in EliminateDeadPhis() 1498 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi() 1511 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi() 2349 MRI.constrainRegClass(NewReg, MRI.getRegClass(OrigReg)); in updateInstrUse()
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H A D | TwoAddressInstructionPass.cpp | 1539 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands() 1661 MRI->constrainRegClass(RegA, RC); in processTiedPairs() 1787 if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) { in processStatepoint()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupSetCC.cpp | 111 if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) { in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MVETPAndVPTOptimisationsPass.cpp | 395 MRI->constrainRegClass(StartReg, &ARM::GPRlrRegClass); in MergeLoopEnd() 396 MRI->constrainRegClass(PhiReg, &ARM::GPRlrRegClass); in MergeLoopEnd() 397 MRI->constrainRegClass(DecReg, &ARM::GPRlrRegClass); in MergeLoopEnd() 530 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
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H A D | Thumb2InstrInfo.cpp | 195 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot() 238 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot() 747 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
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H A D | ARMLoadStoreOptimizer.cpp | 2431 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps() 2432 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps() 3026 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset() 3083 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore() 3086 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
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H A D | A15SDOptimizer.cpp | 635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 150 if (!MRI.constrainRegClass(Src, DstRC, /* MinNumRegs */ 25)) in foldSimpleCrossClassCopies()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 237 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMergeBaseOffset.cpp | 153 MRI->constrainRegClass(Lo.getOperand(0).getReg(), in foldOffset()
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H A D | RISCVOptWInstrs.cpp | 656 if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg))) in removeSExtWInstrs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchOptWInstrs.cpp | 709 if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg))) in removeSExtWInstrs()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 351 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand() 484 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
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