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Searched refs:constrainRegClass (Results 1 – 25 of 52) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp359 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
362 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); in AssignSlot()
365 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); in AssignSlot()
368 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); in AssignSlot()
H A DAMDGPUGlobalISelDivergenceLowering.cpp94 if (MRI->constrainRegClass(DstReg, ST->getBoolRC())) in markAsLaneMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp573 MRI->constrainRegClass(SrcReg, FirstInstrOperandRC); in splitTwoPartImm()
574 MRI->constrainRegClass(NewTmpReg, SecondInstrOperandRC); in splitTwoPartImm()
576 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in splitTwoPartImm()
697 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDef)); in visitINSvi64lane()
716 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDef)); in visitFMOVDr()
828 MRI->constrainRegClass(SrcReg, MRI->getRegClass(InputReg)); in visitCopy()
H A DAArch64ConditionalCompares.cpp641 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
688 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
691 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
H A DAArch64InstrInfo.cpp852 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
858 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
940 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
944 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
948 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
951 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
979 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
980 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
1382 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
3706 MRI.constrainRegClass(AM.BaseReg, &AArch64::GPR64spRegClass); in emitLdStWithAddr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() function
84 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( in constrainRegClass() function in MachineRegisterInfo
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
109 if (!::constrainRegClass( in constrainRegAttrs()
H A DOptimizePHIs.cpp193 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
H A DMachineLoopUtils.cpp67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg())); in PeelSingleBlockLoop()
H A DUnreachableBlockElim.cpp211 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in run()
H A DMachineSSAUpdater.cpp245 if (UseRC && !MRI->constrainRegClass(NewVR, UseRC)) { in RewriteUse()
H A DTargetInstrInfo.cpp1338 MRI.constrainRegClass(RegA, RC); in reassociateOps()
1340 MRI.constrainRegClass(RegB, RC); in reassociateOps()
1342 MRI.constrainRegClass(RegX, RC); in reassociateOps()
1344 MRI.constrainRegClass(RegY, RC); in reassociateOps()
1346 MRI.constrainRegClass(RegC, RC); in reassociateOps()
H A DTailDuplicator.cpp259 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate()
447 : MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
H A DModuloSchedule.cpp1208 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1264 MRI.constrainRegClass(MI.getOperand(1).getReg(), in EliminateDeadPhis()
1517 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1530 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
2375 MRI.constrainRegClass(NewReg, MRI.getRegClass(OrigReg)); in updateInstrUse()
H A DTwoAddressInstructionPass.cpp1541 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands()
1663 MRI->constrainRegClass(RegA, RC); in processTiedPairs()
1789 if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) { in processStatepoint()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp457 MRI->constrainRegClass(True->getOperand(1).getReg(), in convertSameMaskVMergeToVMv()
618 MRI->constrainRegClass(MI.getOperand(2).getReg(), in foldUndefPassthruVMV_V_V()
678 MRI->constrainRegClass(Passthru.getReg(), in foldVMV_V_V()
691 MRI->constrainRegClass(Src->getOperand(0).getReg(), in foldVMV_V_V()
818 MRI->constrainRegClass( in foldVMergeToMask()
H A DRISCVMergeBaseOffset.cpp164 MRI->constrainRegClass(Lo.getOperand(0).getReg(), in foldOffset()
H A DRISCVOptWInstrs.cpp698 if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg))) in removeSExtWInstrs()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp111 if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp393 MRI->constrainRegClass(StartReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
394 MRI->constrainRegClass(PhiReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
395 MRI->constrainRegClass(DecReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
528 MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); in ConvertTailPredLoop()
H A DThumb2InstrInfo.cpp196 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
237 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
749 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
H A DARMLoadStoreOptimizer.cpp2428 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2429 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
3018 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
3075 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
3078 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
H A DA15SDOptimizer.cpp635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp145 if (!MRI.constrainRegClass(Src, DstRC, /* MinNumRegs */ 25)) in foldSimpleCrossClassCopies()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp229 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp349 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
481 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()

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