| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 304 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
326 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
327 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
353 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
509 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
582 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1051 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
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| H A D | ARMCallLowering.cpp | 494 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2024 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
2055 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2077 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2078 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2101 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2102 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2103 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2151 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2196 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 107 Register constrainOperandRegClass(const MachineFunction &MF,
126 Register constrainOperandRegClass(const MachineFunction &MF,
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| H A D | GIMatchTableExecutorImpl.h | 1396 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO); in executeMatchTable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1146 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1148 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1328 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1329 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1373 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1414 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1415 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1458 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1459 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2068 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 284 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(), in optimizeNZCVDefs()
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| H A D | AArch64CallLowering.cpp | 1132 MIB->getOperand(4).setReg(constrainOperandRegClass( in lowerTailCall()
1250 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerTailCall()
1401 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerCall()
1434 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(), in lowerCall()
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| H A D | AArch64InstructionSelector.cpp | 2744 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *NewI, in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 227 constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(), in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 56 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
108 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
151 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
188 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); in constrainSelectedInstRegOperands()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 471 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| H A D | X86FastISel.cpp | 217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
642 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
4023 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
4044 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
4045 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
4046 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
4047 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 390 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 1227 MIB->getOperand(Idx).setReg(constrainOperandRegClass( in lowerTailCall()
1332 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
1505 MIB->getOperand(1).setReg(constrainOperandRegClass( in lowerCall()
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| H A D | AMDGPUInstructionSelector.cpp | 528 SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I, in selectG_EXTRACT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 631 constrainOperandRegClass(MF, *TRI, MF.getRegInfo(), in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2129 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
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