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Searched refs:constrainOperandRegClass (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp329 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
351 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
352 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
378 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
536 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
611 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
691 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1089 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1168 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1306 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
H A DARMCallLowering.cpp494 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1969 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
2000 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2022 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2023 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2046 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2047 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2048 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2073 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2096 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2141 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1141 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1143 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1323 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1324 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1368 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1409 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1410 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1453 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1454 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2064 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h109 LLVM_ABI Register constrainOperandRegClass(
125 LLVM_ABI Register constrainOperandRegClass(
H A DGIMatchTableExecutorImpl.h1450 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO); in executeMatchTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp279 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(), in optimizeNZCVDefs()
H A DAArch64CallLowering.cpp1181 MIB->getOperand(4).setReg(constrainOperandRegClass( in lowerTailCall()
1299 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerTailCall()
1455 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerCall()
1488 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(), in lowerCall()
H A DAArch64InstructionSelector.cpp2873 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *NewI, in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp227 constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(), in lowerCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h468 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp56 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
108 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
151 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
188 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); in constrainSelectedInstRegOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp
H A DX86FastISel.cpp218 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
643 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
4038 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
4059 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
4060 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
4061 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
4062 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp389 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp1275 MIB->getOperand(Idx).setReg(constrainOperandRegClass( in lowerTailCall()
1395 constrainOperandRegClass(MF, *TRI, MRI, *TII, *ST.getRegBankInfo(), in lowerTailCall()
1560 MIB->getOperand(1).setReg(constrainOperandRegClass( in lowerCall()
H A DAMDGPUInstructionSelector.cpp626 SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I, in selectG_EXTRACT()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp650 constrainOperandRegClass(MF, *TRI, MF.getRegInfo(), in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2143 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2144 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()