Lines Matching refs:constrainOperandRegClass

304   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_r()
326 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
327 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
353 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
509 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
582 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1051 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1301 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1432 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1637 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1657 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); in SelectSelect()
1658 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1666 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
2270 constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); in ARMEmitLibcall()
2412 constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); in SelectCall()
2732 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR); in ARMEmitIntExt()
2986 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0); in ARMLowerPICELF()