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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-nominal.dtsi6 &clk {
7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
8 <&clk IMX8MP_CLK_A53_CORE>,
9 <&clk IMX8MP_SYS_PLL3>,
10 <&clk IMX8MP_CLK_NOC>,
11 <&clk IMX8MP_CLK_NOC_IO>,
12 <&clk IMX8MP_CLK_GIC>;
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
14 <&clk IMX8MP_ARM_PLL_OUT>,
16 <&clk IMX8MP_SYS_PLL1_800M>,
[all …]
H A Dimx91.dtsi46 clocks = <&clk IMX93_CLK_TMC_GATE>;
57 &clk {
66 clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
67 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
68 <&clk IMX91_CLK_ENET_TIMER>,
69 <&clk IMX91_CLK_ENET1_QOS_TSN>,
70 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
71 assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
72 <&clk IMX91_CLK_ENET1_QOS_TSN>;
73 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
[all …]
H A Dimx8mq.dtsi109 clocks = <&clk IMX8MQ_CLK_ARM>;
128 clocks = <&clk IMX8MQ_CLK_ARM>;
145 clocks = <&clk IMX8MQ_CLK_ARM>;
162 clocks = <&clk IMX8MQ_CLK_ARM>;
386 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
402 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
418 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
434 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
449 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
486 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
[all …]
H A Dimx8mm.dtsi65 clocks = <&clk IMX8MM_CLK_ARM>;
85 clocks = <&clk IMX8MM_CLK_ARM>;
103 clocks = <&clk IMX8MM_CLK_ARM>;
121 clocks = <&clk IMX8MM_CLK_ARM>;
271 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
272 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
273 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
281 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
282 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
283 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
[all …]
H A Dimx8mn.dtsi65 clocks = <&clk IMX8MN_CLK_ARM>;
85 clocks = <&clk IMX8MN_CLK_ARM>;
103 clocks = <&clk IMX8MN_CLK_ARM>;
121 clocks = <&clk IMX8MN_CLK_ARM>;
296 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
297 <&clk IMX8MN_CLK_DUMMY>,
298 <&clk IMX8MN_CLK_SAI2_ROOT>,
299 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
311 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
312 <&clk IMX8MN_CLK_DUMMY>,
[all …]
H A Dimx8mp.dtsi70 clocks = <&clk IMX8MP_CLK_ARM>;
96 clocks = <&clk IMX8MP_CLK_ARM>;
120 clocks = <&clk IMX8MP_CLK_ARM>;
144 clocks = <&clk IMX8MP_CLK_ARM>;
419 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
435 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
451 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
467 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
482 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
527 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
[all …]
H A Dimx91_93_common.dtsi116 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
123 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
178 clocks = <&clk IMX93_CLK_EDMA1_GATE>;
200 clocks = <&clk IMX93_CLK_WDOG1_GATE>;
209 clocks = <&clk IMX93_CLK_WDOG2_GATE>;
217 clocks = <&clk IMX93_CLK_TPM1_GATE>;
225 clocks = <&clk IMX93_CLK_TPM2_GATE>;
236 clocks = <&clk IMX93_CLK_BUS_AON>,
237 <&clk IMX93_CLK_I3C1_GATE>,
238 <&clk IMX93_CLK_I3C1_SLOW>;
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_pll.c66 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
72 rk_clk_pll_set_gate(struct clknode *clk, bool enable) in rk_clk_pll_set_gate() argument
77 sc = clknode_get_softc(clk); in rk_clk_pll_set_gate()
88 DEVICE_LOCK(clk); in rk_clk_pll_set_gate()
89 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
90 DEVICE_UNLOCK(clk); in rk_clk_pll_set_gate()
120 rk3066_clk_pll_init(struct clknode *clk, device_t dev) in rk3066_clk_pll_init() argument
125 sc = clknode_get_softc(clk); in rk3066_clk_pll_init()
127 DEVICE_LOCK(clk); in rk3066_clk_pll_init()
128 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_init()
[all …]
H A Drk_clk_composite.c68 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
74 rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) in rk_clk_composite_read_4() argument
78 sc = clknode_get_softc(clk); in rk_clk_composite_read_4()
82 CLKDEV_READ_4(clknode_get_device(clk), addr, val); in rk_clk_composite_read_4()
86 rk_clk_composite_write_4(struct clknode *clk, bus_addr_t addr, uint32_t val) in rk_clk_composite_write_4() argument
90 sc = clknode_get_softc(clk); in rk_clk_composite_write_4()
94 CLKDEV_WRITE_4(clknode_get_device(clk), addr, val); in rk_clk_composite_write_4()
98 rk_clk_composite_get_grf(struct clknode *clk) in rk_clk_composite_get_grf() argument
105 dev = clknode_get_device(clk); in rk_clk_composite_get_grf()
117 rk_clk_composite_init(struct clknode *clk, device_t dev) in rk_clk_composite_init() argument
[all …]
H A Drk_clk_mux.c59 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
64 static int rk_clk_mux_init(struct clknode *clk, device_t dev);
65 static int rk_clk_mux_set_mux(struct clknode *clk, int idx);
66 static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent,
88 rk_clk_mux_get_grf(struct clknode *clk) in rk_clk_mux_get_grf() argument
95 dev = clknode_get_device(clk); in rk_clk_mux_get_grf()
107 rk_clk_mux_init(struct clknode *clk, device_t dev) in rk_clk_mux_init() argument
113 sc = clknode_get_softc(clk); in rk_clk_mux_init()
116 sc->grf = rk_clk_mux_get_grf(clk); in rk_clk_mux_init()
119 clknode_get_name(clk)); in rk_clk_mux_init()
[all …]
H A Drk_clk_fract.c51 static int rk_clk_fract_init(struct clknode *clk, device_t dev);
52 static int rk_clk_fract_recalc(struct clknode *clk, uint64_t *req);
55 static int rk_clk_fract_set_gate(struct clknode *clk, bool enable);
138 rk_clk_fract_init(struct clknode *clk, device_t dev) in rk_clk_fract_init() argument
143 sc = clknode_get_softc(clk); in rk_clk_fract_init()
144 DEVICE_LOCK(clk); in rk_clk_fract_init()
145 RD4(clk, sc->offset, &reg); in rk_clk_fract_init()
146 DEVICE_UNLOCK(clk); in rk_clk_fract_init()
152 clknode_init_parent_idx(clk, 0); in rk_clk_fract_init()
158 rk_clk_fract_set_gate(struct clknode *clk, bool enable) in rk_clk_fract_set_gate() argument
[all …]
H A Drk_clk_armclk.c73 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
79 rk_clk_armclk_init(struct clknode *clk, device_t dev) in rk_clk_armclk_init() argument
84 sc = clknode_get_softc(clk); in rk_clk_armclk_init()
87 DEVICE_LOCK(clk); in rk_clk_armclk_init()
88 READ4(clk, sc->muxdiv_offset, &val); in rk_clk_armclk_init()
89 DEVICE_UNLOCK(clk); in rk_clk_armclk_init()
93 clknode_init_parent_idx(clk, idx); in rk_clk_armclk_init()
99 rk_clk_armclk_set_mux(struct clknode *clk, int index) in rk_clk_armclk_set_mux() argument
104 sc = clknode_get_softc(clk); in rk_clk_armclk_set_mux()
107 DEVICE_LOCK(clk); in rk_clk_armclk_set_mux()
[all …]
/freebsd/sys/dev/clk/xilinx/
H A Dzynqmp_clock.c113 struct zynqmp_clk *clk; member
119 zynqmp_clk_init(struct clknode *clk, device_t dev) in zynqmp_clk_init() argument
122 clknode_init_parent_idx(clk, 0); in zynqmp_clk_init()
219 sc->clk = clkdef; in zynqmp_clk_register()
225 zynqmp_fw_clk_get_name(struct zynqmp_clock_softc *sc, struct zynqmp_clk *clk, uint32_t id) in zynqmp_fw_clk_get_name() argument
238 clk->clkdef.name = clkname; in zynqmp_fw_clk_get_name()
243 zynqmp_fw_clk_get_attributes(struct zynqmp_clock_softc *sc, struct zynqmp_clk *clk, uint32_t id) in zynqmp_fw_clk_get_attributes() argument
251 clk->attributes = query_data[1]; in zynqmp_fw_clk_get_attributes()
256 zynqmp_fw_clk_get_parents(struct zynqmp_clock_softc *sc, struct zynqmp_clk *clk, uint32_t id) in zynqmp_fw_clk_get_parents() argument
262 clk->parentids[i] = -1; in zynqmp_fw_clk_get_parents()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,flexgen.txt85 clk_s_c0_flexgen: clk-s-c0-flexgen {
98 clock-output-names = "clk-icn-gpu",
99 "clk-fdma",
100 "clk-nand",
101 "clk-hva",
102 "clk-proc-stfe",
103 "clk-proc-tp",
104 "clk-rx-icn-dmu",
105 "clk-rx-icn-hva",
106 "clk-icn-cpu",
[all …]
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_composite.c69 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
75 imx_clk_composite_init(struct clknode *clk, device_t dev) in imx_clk_composite_init() argument
80 sc = clknode_get_softc(clk); in imx_clk_composite_init()
82 DEVICE_LOCK(clk); in imx_clk_composite_init()
83 READ4(clk, sc->offset, &val); in imx_clk_composite_init()
84 DEVICE_UNLOCK(clk); in imx_clk_composite_init()
87 clknode_init_parent_idx(clk, idx); in imx_clk_composite_init()
93 imx_clk_composite_set_gate(struct clknode *clk, bool enable) in imx_clk_composite_set_gate() argument
98 sc = clknode_get_softc(clk); in imx_clk_composite_set_gate()
101 DEVICE_LOCK(clk); in imx_clk_composite_set_gate()
[all …]
H A Dimx_clk_sscg_pll.c71 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
77 imx_clk_sscg_pll_init(struct clknode *clk, device_t dev) in imx_clk_sscg_pll_init() argument
79 if (clknode_get_parents_num(clk) > 1) { in imx_clk_sscg_pll_init()
80 device_printf(clknode_get_device(clk), in imx_clk_sscg_pll_init()
84 clknode_init_parent_idx(clk, 0); in imx_clk_sscg_pll_init()
90 imx_clk_sscg_pll_set_gate(struct clknode *clk, bool enable) in imx_clk_sscg_pll_set_gate() argument
96 sc = clknode_get_softc(clk); in imx_clk_sscg_pll_set_gate()
98 DEVICE_LOCK(clk); in imx_clk_sscg_pll_set_gate()
99 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
104 WRITE4(clk, sc->offset + CFG0, cfg0); in imx_clk_sscg_pll_set_gate()
[all …]
H A Dimx_clk_mux.c54 static int imx_clk_mux_init(struct clknode *clk, device_t dev);
55 static int imx_clk_mux_set_mux(struct clknode *clk, int idx);
74 imx_clk_mux_init(struct clknode *clk, device_t dev) in imx_clk_mux_init() argument
80 sc = clknode_get_softc(clk); in imx_clk_mux_init()
82 DEVICE_LOCK(clk); in imx_clk_mux_init()
83 rv = RD4(clk, sc->offset, &reg); in imx_clk_mux_init()
84 DEVICE_UNLOCK(clk); in imx_clk_mux_init()
89 clknode_init_parent_idx(clk, reg); in imx_clk_mux_init()
94 imx_clk_mux_set_mux(struct clknode *clk, int idx) in imx_clk_mux_set_mux() argument
100 sc = clknode_get_softc(clk); in imx_clk_mux_set_mux()
[all …]
H A Dimx_clk_frac_pll.c67 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
73 imx_clk_frac_pll_init(struct clknode *clk, device_t dev) in imx_clk_frac_pll_init() argument
76 clknode_init_parent_idx(clk, 0); in imx_clk_frac_pll_init()
81 imx_clk_frac_pll_set_gate(struct clknode *clk, bool enable) in imx_clk_frac_pll_set_gate() argument
87 sc = clknode_get_softc(clk); in imx_clk_frac_pll_set_gate()
89 DEVICE_LOCK(clk); in imx_clk_frac_pll_set_gate()
90 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
95 WRITE4(clk, sc->offset + CFG0, cfg0); in imx_clk_frac_pll_set_gate()
100 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
107 DEVICE_UNLOCK(clk); in imx_clk_frac_pll_set_gate()
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Daw_clk_m.c69 aw_clk_m_init(struct clknode *clk, device_t dev) in aw_clk_m_init() argument
74 sc = clknode_get_softc(clk); in aw_clk_m_init()
78 DEVICE_LOCK(clk); in aw_clk_m_init()
79 READ4(clk, sc->offset, &val); in aw_clk_m_init()
80 DEVICE_UNLOCK(clk); in aw_clk_m_init()
85 clknode_init_parent_idx(clk, idx); in aw_clk_m_init()
90 aw_clk_m_set_gate(struct clknode *clk, bool enable) in aw_clk_m_set_gate() argument
95 sc = clknode_get_softc(clk); in aw_clk_m_set_gate()
100 DEVICE_LOCK(clk); in aw_clk_m_set_gate()
101 READ4(clk, sc->offset, &val); in aw_clk_m_set_gate()
[all …]
H A Dccu_d1.c957 { .type = AW_CLK_NP, .clk.np = &pll_cpux_clk },
958 { .type = AW_CLK_NMM, .clk.nmm = &pll_ddr0_clk },
959 { .type = AW_CLK_NMM, .clk.nmm = &pll_periph0_4x_clk },
960 { .type = AW_CLK_M, .clk.m = &pll_periph0_2x_clk },
961 { .type = AW_CLK_M, .clk.m = &pll_periph0_800m_clk },
962 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_clk },
963 { .type = AW_CLK_NP, .clk.np = &pll_video0_clk },
964 { .type = AW_CLK_M, .clk.m = &pll_video0_4x_clk },
965 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk },
966 { .type = AW_CLK_NP, .clk.np = &pll_video1_clk },
[all …]
H A Dccu_a31.c866 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpu_clk},
867 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
868 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk},
869 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
870 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_mipi_clk},
871 { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk},
872 { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
873 { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
874 { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
875 { .type = AW_CLK_FRAC, .clk.frac = &pll9_clk},
[all …]
/freebsd/sys/dev/clk/
H A Dclk.h58 typedef struct clk *clk_t;
94 struct clknode *clknode_register(struct clkdom *cldom, struct clknode *clk);
97 phandle_t *cells, struct clknode **clk);
102 int clknode_set_parent_by_idx(struct clknode *clk, int idx);
103 int clknode_set_parent_by_name(struct clknode *clk, const char *name);
104 const char *clknode_get_name(struct clknode *clk);
105 const char **clknode_get_parent_names(struct clknode *clk);
106 int clknode_get_parents_num(struct clknode *clk);
107 int clknode_get_parent_idx(struct clknode *clk);
108 struct clknode *clknode_get_parent(struct clknode *clk);
[all …]
H A Dclk_gate.c50 static int clknode_gate_init(struct clknode *clk, device_t dev);
51 static int clknode_gate_set_gate(struct clknode *clk, bool enable);
52 static int clknode_gate_get_gate(struct clknode *clk, bool *enable);
73 clknode_gate_init(struct clknode *clk, device_t dev) in clknode_gate_init() argument
76 clknode_init_parent_idx(clk, 0); in clknode_gate_init()
81 clknode_gate_set_gate(struct clknode *clk, bool enable) in clknode_gate_set_gate() argument
87 sc = clknode_get_softc(clk); in clknode_gate_set_gate()
88 DEVICE_LOCK(clk); in clknode_gate_set_gate()
89 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in clknode_gate_set_gate()
92 DEVICE_UNLOCK(clk); in clknode_gate_set_gate()
[all …]
H A Dclk_link.c42 static int clknode_link_init(struct clknode *clk, device_t dev);
43 static int clknode_link_recalc(struct clknode *clk, uint64_t *freq);
44 static int clknode_link_set_freq(struct clknode *clk, uint64_t fin,
46 static int clknode_link_set_mux(struct clknode *clk, int idx);
47 static int clknode_link_set_gate(struct clknode *clk, bool enable);
62 clknode_link_init(struct clknode *clk, device_t dev) in clknode_link_init() argument
68 clknode_link_recalc(struct clknode *clk, uint64_t *freq) in clknode_link_recalc() argument
72 clknode_get_name(clk)); in clknode_link_recalc()
77 clknode_link_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, in clknode_link_set_freq() argument
82 clknode_get_name(clk)); in clknode_link_set_freq()
[all …]
H A Dclk_mux.c50 static int clknode_mux_init(struct clknode *clk, device_t dev);
51 static int clknode_mux_set_mux(struct clknode *clk, int idx);
71 clknode_mux_init(struct clknode *clk, device_t dev) in clknode_mux_init() argument
77 sc = clknode_get_softc(clk); in clknode_mux_init()
79 DEVICE_LOCK(clk); in clknode_mux_init()
80 rv = RD4(clk, sc->offset, &reg); in clknode_mux_init()
81 DEVICE_UNLOCK(clk); in clknode_mux_init()
86 clknode_init_parent_idx(clk, reg); in clknode_mux_init()
91 clknode_mux_set_mux(struct clknode *clk, int idx) in clknode_mux_set_mux() argument
97 sc = clknode_get_softc(clk); in clknode_mux_set_mux()
[all …]

12345678910>>...59