Lines Matching refs:clk
66 clocks = <&clk IMX8MN_CLK_ARM>;
87 clocks = <&clk IMX8MN_CLK_ARM>;
106 clocks = <&clk IMX8MN_CLK_ARM>;
125 clocks = <&clk IMX8MN_CLK_ARM>;
301 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
302 <&clk IMX8MN_CLK_DUMMY>,
303 <&clk IMX8MN_CLK_SAI2_ROOT>,
304 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
316 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
317 <&clk IMX8MN_CLK_DUMMY>,
318 <&clk IMX8MN_CLK_SAI3_ROOT>,
319 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
331 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
332 <&clk IMX8MN_CLK_DUMMY>,
333 <&clk IMX8MN_CLK_SAI5_ROOT>,
334 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
348 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
349 <&clk IMX8MN_CLK_DUMMY>,
350 <&clk IMX8MN_CLK_SAI6_ROOT>,
351 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
365 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
366 <&clk IMX8MN_CLK_PDM_ROOT>,
367 <&clk IMX8MN_AUDIO_PLL1_OUT>,
368 <&clk IMX8MN_AUDIO_PLL2_OUT>,
369 <&clk IMX8MN_CLK_EXT3>;
382 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
383 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
384 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
386 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
387 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
388 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
389 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
390 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
391 <&clk IMX8MN_CLK_DUMMY>; /* spba */
407 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
408 <&clk IMX8MN_CLK_DUMMY>,
409 <&clk IMX8MN_CLK_SAI7_ROOT>,
410 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
421 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
443 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
456 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
469 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
482 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
495 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
506 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
516 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
524 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
532 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
540 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
541 <&clk IMX8MN_CLK_SDMA3_ROOT>;
551 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
552 <&clk IMX8MN_CLK_SDMA2_ROOT>;
571 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
621 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
629 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
637 clk: clock-controller@30380000 {
647 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
648 <&clk IMX8MN_CLK_A53_CORE>,
649 <&clk IMX8MN_CLK_NOC>,
650 <&clk IMX8MN_CLK_AUDIO_AHB>,
651 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
652 <&clk IMX8MN_SYS_PLL3>,
653 <&clk IMX8MN_AUDIO_PLL1>,
654 <&clk IMX8MN_AUDIO_PLL2>;
655 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
656 <&clk IMX8MN_ARM_PLL_OUT>,
657 <&clk IMX8MN_SYS_PLL3_OUT>,
658 <&clk IMX8MN_SYS_PLL1_800M>;
687 clocks = <&clk IMX8MN_CLK_USB_BUS>;
698 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
699 <&clk IMX8MN_CLK_GPU_SHADER>,
700 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
701 <&clk IMX8MN_CLK_GPU_AHB>;
707 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
708 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
731 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
732 <&clk IMX8MN_CLK_PWM1_ROOT>;
742 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
743 <&clk IMX8MN_CLK_PWM2_ROOT>;
753 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
754 <&clk IMX8MN_CLK_PWM3_ROOT>;
764 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
765 <&clk IMX8MN_CLK_PWM4_ROOT>;
800 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
801 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
814 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
815 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
828 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
829 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
840 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
841 <&clk IMX8MN_CLK_UART1_ROOT>;
852 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
853 <&clk IMX8MN_CLK_UART3_ROOT>;
864 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
865 <&clk IMX8MN_CLK_UART2_ROOT>;
878 clocks = <&clk IMX8MN_CLK_AHB>,
879 <&clk IMX8MN_CLK_IPG_ROOT>;
908 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
918 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
928 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
938 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
946 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
947 <&clk IMX8MN_CLK_UART4_ROOT>;
958 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
966 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
967 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
968 <&clk IMX8MN_CLK_USDHC1_ROOT>;
980 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
981 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
982 <&clk IMX8MN_CLK_USDHC2_ROOT>;
994 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
995 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
996 <&clk IMX8MN_CLK_USDHC3_ROOT>;
1011 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
1012 <&clk IMX8MN_CLK_QSPI_ROOT>;
1021 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
1022 <&clk IMX8MN_CLK_AHB>;
1035 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1036 <&clk IMX8MN_CLK_ENET1_ROOT>,
1037 <&clk IMX8MN_CLK_ENET_TIMER>,
1038 <&clk IMX8MN_CLK_ENET_REF>,
1039 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1042 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1043 <&clk IMX8MN_CLK_ENET_TIMER>,
1044 <&clk IMX8MN_CLK_ENET_REF>,
1045 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1046 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1047 <&clk IMX8MN_SYS_PLL2_100M>,
1048 <&clk IMX8MN_SYS_PLL2_125M>,
1049 <&clk IMX8MN_SYS_PLL2_50M>;
1071 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1072 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1073 <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
1089 clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1090 <&clk IMX8MN_CLK_DSI_PHY_REF>;
1114 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1115 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
1143 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1144 <&clk IMX8MN_CLK_DISP_APB>,
1145 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1146 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1147 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1148 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1149 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1150 <&clk IMX8MN_CLK_DSI_CORE>,
1151 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1152 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1153 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1159 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1160 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1161 <&clk IMX8MN_CLK_DISP_PIXEL>,
1162 <&clk IMX8MN_CLK_DISP_AXI>,
1163 <&clk IMX8MN_CLK_DISP_APB>;
1164 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1165 <&clk IMX8MN_CLK_24M>,
1166 <&clk IMX8MN_VIDEO_PLL1_OUT>,
1167 <&clk IMX8MN_SYS_PLL2_1000M>,
1168 <&clk IMX8MN_SYS_PLL1_800M>;
1181 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
1182 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
1185 clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1186 <&clk IMX8MN_CLK_CAMERA_PIXEL>,
1187 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1188 <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
1215 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1217 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1218 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1242 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1253 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1254 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1265 clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1266 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1267 <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1268 <&clk IMX8MN_CLK_GPU_SHADER>;
1270 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1271 <&clk IMX8MN_CLK_GPU_SHADER>,
1272 <&clk IMX8MN_CLK_GPU_AXI>,
1273 <&clk IMX8MN_CLK_GPU_AHB>,
1274 <&clk IMX8MN_GPU_PLL>;
1275 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1276 <&clk IMX8MN_GPU_PLL_OUT>,
1277 <&clk IMX8MN_SYS_PLL1_800M>,
1278 <&clk IMX8MN_SYS_PLL1_800M>;
1300 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1301 <&clk IMX8MN_DRAM_PLL>,
1302 <&clk IMX8MN_CLK_DRAM_ALT>,
1303 <&clk IMX8MN_CLK_DRAM_APB>;
1316 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1317 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1318 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;