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Searched refs:buildUndef (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperVectorOps.cpp84 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchExtractVectorElement()
305 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchExtractVectorElementWithShuffleVector()
358 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchInsertVectorElementOOB()
H A DMachineIRBuilder.cpp261 buildUndef(Op0Ty.isVector() ? Op0Ty.getElementType() : Op0Ty).getReg(0); in buildPadVectorWithUndefElements()
643 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder
766 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
H A DCombinerHelper.cpp343 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()
387 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()
422 Extracts.push_back(Builder.buildUndef(EltTy).getReg(0)); in applyCombineShuffleToBuildVector()
510 UndefReg = Builder.buildUndef(SrcTy).getReg(0); in applyCombineShuffleConcat()
596 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
646 Builder.buildUndef(DstReg); in applyShuffleToExtract()
2315 B.buildUndef(DstReg); in matchCombineUnmergeUndef()
3042 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()
3120 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
3531 Register UndefReg = Builder.buildUndef(UnmergeSrcTy).getReg(0); in applyUseVectorTruncate()
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H A DLegalizerHelper.cpp275 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
320 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
1507 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()
1518 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()
2235 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()
5241 MIRBuilder.buildUndef(DstReg); in fewerElementsVectorExtractInsertVectorElt()
5694 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); in fewerElementsVectorShuffle()
5713 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); in fewerElementsVectorShuffle()
5718 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) in fewerElementsVectorShuffle()
6279 Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType())); in moreElementsVector()
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H A DIRTranslator.cpp1832 auto Undef = MIRBuilder.buildUndef(MRI->getType(Op)); in translateVectorDeinterleave2Intrinsic()
2441 MIRBuilder.buildUndef(getOrCreateVReg(CI)); in translateKnownIntrinsic()
3050 MIRBuilder.buildUndef(Undef); in translateLandingPad()
3665 EntryBuilder->buildUndef(Reg); in translate()
H A DCallLowering.cpp634 Register Undef = B.buildUndef(SrcTy).getReg(0); in buildCopyToRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp656 B.buildUndef(R); in lowerFormalArguments()
834 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
839 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
928 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
H A DAMDGPURegBankLegalize.cpp218 {TruncSrc, B.buildUndef({SgprRB, S32})}); in tryCombineS1AnyExt()
H A DAMDGPULegalizerInfo.cpp2466 B.buildUndef(Dst); in legalizeAddrSpaceCast()
2803 B.buildUndef(Dst); in legalizeExtractVectorElt()
2864 B.buildUndef(Dst); in legalizeInsertVectorElt()
3034 B.buildUndef(DstReg); in legalizeGlobalValue()
4404 B.buildUndef(DstReg); in loadInputValue()
4448 B.buildUndef(DstReg); in legalizeWorkitemIDIntrinsic()
5847 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()
5857 PackedRegs.resize(6, B.buildUndef(S16).getReg(0)); in handleD16VData()
5868 PackedRegs.resize(4, B.buildUndef(S32).getReg(0)); in handleD16VData()
6370 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
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H A DAMDGPURegBankLegalizeHelper.cpp159 Hi = B.buildUndef({VgprRB_S32}); in lowerVccExtToSel()
427 Hi = B.buildUndef({RB, S32}); in lower()
H A DAMDGPURegisterBankInfo.cpp1945 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1025 buildSplatSplitS64WithVL(Dst, MIB.buildUndef(VecTy), SplatVal, VL, MIB, in legalizeSplatVector()
1149 {MIB.buildUndef(InterLitTy), Vec, SlidedownAmt, Mask, VL, Policy}); in legalizeExtractSubvector()
1245 auto Insert = MIB.buildInsertSubvector(InterLitTy, MIB.buildUndef(InterLitTy), in legalizeInsertSubvector()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp776 auto Undef = B.buildUndef(SrcTy); in applyDupLane()
1063 Register DstReg = B.buildUndef(DstTy).getReg(0); in applyLowerBuildToInsertVecElt()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h396 auto Impl = Builder.buildUndef(DstTy); in tryFoldImplicitDef()
H A DMachineIRBuilder.h1064 MachineInstrBuilder buildUndef(const DstOp &Res);