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Searched refs:buildUndef (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperVectorOps.cpp84 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchExtractVectorElement()
345 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchExtractVectorElementWithShuffleVector()
398 MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; in matchInsertVectorElementOOB()
H A DMachineIRBuilder.cpp261 buildUndef(Op0Ty.isVector() ? Op0Ty.getElementType() : Op0Ty).getReg(0); in buildPadVectorWithUndefElements()
640 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder
754 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
H A DLegalizerHelper.cpp275 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
320 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
1244 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()
1255 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()
1937 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()
4565 MIRBuilder.buildUndef(DstReg); in fewerElementsVectorExtractInsertVectorElt()
5005 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); in fewerElementsVectorShuffle()
5024 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); in fewerElementsVectorShuffle()
5029 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) in fewerElementsVectorShuffle()
5585 Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType())); in moreElementsVector()
[all …]
H A DCombinerHelper.cpp325 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()
369 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()
444 UndefReg = Builder.buildUndef(SrcTy).getReg(0); in applyCombineShuffleConcat()
530 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
580 Builder.buildUndef(DstReg); in applyShuffleToExtract()
2216 B.buildUndef(DstReg); in matchCombineUnmergeUndef()
3011 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()
3085 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
7256 B.buildUndef(Carry); in matchAddOverflow()
H A DIRTranslator.cpp1824 auto Undef = MIRBuilder.buildUndef(MRI->getType(Op)); in translateVectorDeinterleave2Intrinsic()
2405 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()
3003 MIRBuilder.buildUndef(Undef); in translateLandingPad()
3508 EntryBuilder->buildUndef(Reg); in translate()
H A DCallLowering.cpp635 Register Undef = B.buildUndef(SrcTy).getReg(0); in buildCopyToRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp654 B.buildUndef(R); in lowerFormalArguments()
832 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
837 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
925 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
H A DAMDGPULegalizerInfo.cpp2416 B.buildUndef(Dst); in legalizeAddrSpaceCast()
2745 B.buildUndef(Dst); in legalizeExtractVectorElt()
2806 B.buildUndef(Dst); in legalizeInsertVectorElt()
2976 B.buildUndef(DstReg); in legalizeGlobalValue()
4347 B.buildUndef(DstReg); in loadInputValue()
4390 B.buildUndef(DstReg); in legalizeWorkitemIDIntrinsic()
5741 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()
5751 PackedRegs.resize(6, B.buildUndef(S16).getReg(0)); in handleD16VData()
5762 PackedRegs.resize(4, B.buildUndef(S32).getReg(0)); in handleD16VData()
6240 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
[all …]
H A DAMDGPURegisterBankInfo.cpp1917 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp730 buildSplatSplitS64WithVL(Dst, MIB.buildUndef(VecTy), SplatVal, VL, MIB, in legalizeSplatVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp758 auto Undef = B.buildUndef(SrcTy); in applyDupLane()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1010 MachineInstrBuilder buildUndef(const DstOp &Res);