Lines Matching refs:buildUndef

275       PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);  in buildLCMMergePieces()
320         AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);  in buildLCMMergePieces()
1244       Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0);  in narrowScalar()
1255       DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));  in narrowScalar()
1937     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);  in widenScalarMergeValues()
4565       MIRBuilder.buildUndef(DstReg);  in fewerElementsVectorExtractInsertVectorElt()
5005           SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0));  in fewerElementsVectorShuffle()
5024       Output = MIRBuilder.buildUndef(NarrowTy).getReg(0);  in fewerElementsVectorShuffle()
5029                          ? MIRBuilder.buildUndef(NarrowTy).getReg(0)  in fewerElementsVectorShuffle()
5585       Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType()));  in moreElementsVector()
5728   auto Undef = MIRBuilder.buildUndef(SrcTy);  in equalizeVectorShuffleLengths()
7612         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);  in lowerShuffleVector()