/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CallLowering.cpp | 414 B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg)); in buildCopyFromRegs() 418 B.buildTrunc(OrigRegs[0], SrcReg); in buildCopyFromRegs() 431 B.buildTrunc(OrigRegs[0], Widened); in buildCopyFromRegs() 502 Merge = B.buildTrunc(RealDstEltTy, Merge); in buildCopyFromRegs() 549 B.buildTrunc(OrigRegs[0], BuildVec); in buildCopyFromRegs() 1397 MIRBuilder.buildTrunc(ValVReg, Hint); in assignValueToReg()
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H A D | LegalizerHelper.cpp | 363 MIRBuilder.buildTrunc(DstReg, Remerge); in buildWidenedRemergeToDst() 1415 MIRBuilder.buildTrunc(TmpReg, SrcReg); in narrowScalar() 1625 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); in narrowScalar() 1792 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); in narrowScalarSrc() 1886 MIRBuilder.buildTrunc(DstReg, ResultReg); in widenScalarMergeValues() 1958 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); in widenScalarMergeValues() 2007 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); in widenScalarUnmergeValues() 2011 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); in widenScalarUnmergeValues() 2122 MIRBuilder.buildTrunc(DstReg, in widenScalarExtract() 2137 MIRBuilder.buildTrunc(DstReg, LShr); in widenScalarExtract() [all …]
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H A D | CombinerHelperVectorOps.cpp | 270 B.buildTrunc(Dst, Build->getSourceReg(MaybeIndex->Value.getZExtValue())); in matchExtractVectorElementWithBuildVectorTrunc()
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H A D | InlineAsmLowering.cpp | 594 MIRBuilder.buildTrunc(ResRegs[i], Tmp1Reg); in lowerInlineAsm()
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H A D | CombinerHelper.cpp | 801 MachineInstr *NewMI = Builder.buildTrunc(NewDstReg, ChosenDstReg); in applyCombineExtendingLoads() 2239 Builder.buildTrunc(Dst0Reg, SrcReg); in applyCombineUnmergeWithDeadLanesToTrunc() 2615 Builder.buildTrunc(DstReg, SrcReg); in applyCombineTruncOfExt() 2707 ShiftSrc = Builder.buildTrunc(NewShiftTy, ShiftSrc).getReg(0); in applyCombineTruncOfShift() 2717 Builder.buildTrunc(Dst, NewShift); in applyCombineTruncOfShift() 4164 Builder.buildTrunc(DstReg, Reg); in applyExtractVecEltBuildVec() 5045 auto NarrowLHS = Builder.buildTrunc(NarrowTy, BinOpLHS); in matchNarrowBinopFeedingAnd() 5046 auto NarrowRHS = Builder.buildTrunc(NarrowTy, BinOpRHS); in matchNarrowBinopFeedingAnd() 7480 B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoSWrap); in matchSextOfTrunc() 7513 B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoUWrap); in matchZextOfTrunc()
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H A D | LoadStoreOpt.cpp | 882 WideSrcVal = Builder.buildTrunc(WideStoreTy, WideSrcVal).getReg(0); in mergeTruncStore()
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H A D | MachineIRBuilder.cpp | 887 MachineIRBuilder::buildTrunc(const DstOp &Res, const SrcOp &Op, in buildTrunc() function in MachineIRBuilder
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.cpp | 276 MIRBuilder.buildTrunc(ValVReg, LoadVReg); in assignValueToAddress() 313 MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg); in assignValueToReg()
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H A D | ARMLegalizerInfo.cpp | 422 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); in legalizeCustom()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsLegalizerInfo.cpp | 405 MIRBuilder.buildTrunc(Val, Load.getReg(0)); in legalizeCustom() 420 MIRBuilder.buildTrunc(Val, Merge); in legalizeCustom()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPreLegalizerCombiner.cpp | 206 B.buildTrunc(MI.getOperand(0).getReg(), Med3); in applyClampI64ToI16()
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H A D | AMDGPURegisterBankInfo.cpp | 1123 B.buildTrunc(MI.getOperand(0), WideLoad); in applyMappingLoad() 1637 Carry = B.buildTrunc(S1, Carry).getReg(0); in applyMappingMAD_64_32() 1695 B.buildTrunc(Dst1, Carry); in applyMappingMAD_64_32() 2211 B.buildTrunc(DefRegs[0], NewDstReg); in applyMappingImpl() 2304 B.buildTrunc(DefRegs[0], NewDstReg); in applyMappingImpl() 2586 B.buildTrunc(Op0L, SrcReg0); in applyMappingImpl() 2592 B.buildTrunc(Op1L, SrcReg1); in applyMappingImpl() 2779 B.buildTrunc(DstReg, Sel); in applyMappingImpl()
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H A D | AMDGPULegalizerInfo.cpp | 3129 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad() 3847 Src0 = B.buildTrunc(S16, MI.getOperand(1).getReg()).getReg(0); in legalizeBuildVector() 3848 Src1 = B.buildTrunc(S16, MI.getOperand(2).getReg()).getReg(0); in legalizeBuildVector() 4203 B.buildTrunc(Dst, Ctlz); in legalizeCTLZ_ZERO_UNDEF() 5487 B.buildTrunc(DstReg, LaneOpDst); in legalizeLaneOp() 6018 B.buildTrunc(Dst, ExtDst); in legalizeBufferLoad() 6036 B.buildTrunc(Dst, LoadDstReg); in legalizeBufferLoad() 6047 Repack.push_back(B.buildTrunc(EltTy, Unmerge.getReg(I)).getReg(0)); in legalizeBufferLoad() 6641 B.buildTrunc(DstReg, ResultRegs[0]); in legalizeImageIntrinsic() 6664 Reg = B.buildTrunc(S16, Reg).getReg(0); in legalizeImageIntrinsic() [all …]
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H A D | AMDGPUCallLowering.cpp | 133 MIRBuilder.buildTrunc(ValVReg, Extended); in assignValueToReg()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 304 Builder.buildTrunc(DstReg, MergeSrcReg); in tryCombineTrunc() 350 Builder.buildTrunc(DstReg, TruncSrc); in tryCombineTrunc() 464 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I)); in tryFoldUnmergeCast()
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H A D | MachineIRBuilder.h | 1242 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PreLegalizerCombiner.cpp | 529 B.buildTrunc({MidScalarLLT}, {extractReg}).getReg(0); in applyExtUaddvToUaddlv()
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H A D | AArch64CallLowering.cpp | 723 MIRBuilder.buildTrunc( in lowerFormalArguments()
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H A D | AArch64LegalizerInfo.cpp | 1643 MIB.buildTrunc(DstReg, ExtReg); in legalizeIntrinsic()
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