| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelperArtifacts.cpp | 54 B.buildAnyExt(Dst, Merge->getSourceReg(0)); in matchMergeXAndUndef()
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| H A D | CallLowering.cpp | 537 BVRegs.push_back(B.buildAnyExt(PartLLT, Unmerge.getReg(K)).getReg(0)); in buildCopyFromRegs()
577 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i)); in buildCopyToRegs()
604 auto Ext = B.buildAnyExt(ExtTy, SrcReg); in buildCopyToRegs()
1323 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
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| H A D | InlineAsmLowering.cpp | 208 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0); in buildAnyextOrCopy()
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| H A D | LegalizerHelper.cpp | 1508 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); in narrowScalar()
1628 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
2298 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in widenScalarUnmergeValues()
2327 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); in widenScalarUnmergeValues()
2429 Src = MIRBuilder.buildAnyExt(WideTy, Src); in widenScalarExtract()
2585 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); in widenScalarAddSubShlSat()
2587 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); in widenScalarAddSubShlSat()
4223 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in lowerStore()
6816 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); in narrowScalarInsert()
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| H A D | MachineIRBuilder.cpp | 497 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, in buildAnyExt() function in MachineIRBuilder
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| H A D | CombinerHelper.cpp | 7986 auto AnyExt = B.buildAnyExt(SmallBvElemenTy, SourceArray); in matchUnmergeValuesAnyExtBuildVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankLegalizeHelper.cpp | 852 auto Aext = B.buildAnyExt(SgprRB_S32, Reg); in applyMappingSrc()
931 auto Aext = B.buildAnyExt(SgprRB_S32, Reg); in applyMappingSrc()
939 auto Aext = B.buildAnyExt(SgprRB_S32, Reg); in applyMappingSrc()
1002 auto NewUse = B.buildAnyExt(SgprRB_S32, UseReg); in applyMappingPHI()
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| H A D | AMDGPURegBankLegalize.cpp | 224 B.buildAnyExt(Dst, TruncSrc); in tryCombineS1AnyExt()
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| H A D | AMDGPURegBankCombiner.cpp | 383 auto NewExt = B.buildAnyExt(ExtAmtTy, AmtReg); in applyCanonicalizeZextShiftAmt()
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| H A D | AMDGPUPostLegalizerCombiner.cpp | 354 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
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| H A D | AMDGPULegalizerInfo.cpp | 4054 Tmp = B.buildAnyExt(S64, LocalAccum[0]).getReg(0); in buildMultiply()
4258 auto Extend = B.buildAnyExt(S32, {Src}).getReg(0u); in legalizeCTLZ_ZERO_UNDEF()
5579 Src0 = B.buildAnyExt(S32, Src0).getReg(0); in legalizeLaneOp()
5582 Src1 = B.buildAnyExt(LLT::scalar(32), Src1).getReg(0); in legalizeLaneOp()
5585 Src2 = B.buildAnyExt(LLT::scalar(32), Src2).getReg(0); in legalizeLaneOp()
5696 auto ExtStride = B.buildAnyExt(S32, Stride); in legalizePointerAsRsrcIntrin()
5834 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
5901 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0); in fixStoreSourceType()
7254 V2S32, {RayExtent, B.buildAnyExt(S32, InstanceMask)}); in legalizeBVHDualOrBVH8IntersectRayIntrinsic()
7636 MI.getOperand(5).setReg(B.buildAnyExt(S32, Index).getReg(0)); in legalizeIntrinsic()
[all …]
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| H A D | AMDGPUCallLowering.cpp | 38 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 376 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); in legalizeCustom()
378 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); in legalizeCustom()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 377 auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg()); in applyMappingImpl()
395 ConstReg = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(1).getReg()) in applyMappingImpl()
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| H A D | AArch64LegalizerInfo.cpp | 1683 Register ExtValueReg = MIB.buildAnyExt(LLT::scalar(64), Value).getReg(0); in legalizeIntrinsic()
2273 MIRBuilder.buildAnyExt(LLT::scalar(64), Value).getReg(0); in legalizeMemOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 111 auto Trunc = MIRBuilder.buildAnyExt(LLT(VA.getLocVT()), Arg.Regs[0]); in assignCustomValue()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 686 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
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