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Searched refs:banks (Results 1 – 25 of 61) sorted by relevance

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/freebsd/sys/dev/ice/
H A Dice_nvm.c462 struct ice_bank_info *banks = &hw->flash.banks;
469 offset = banks->nvm_ptr; in ice_get_flash_bank_offset()
470 size = banks->nvm_size; in ice_get_flash_bank_offset()
471 active_bank = banks->nvm_bank; in ice_get_flash_bank_offset()
474 offset = banks->orom_ptr; in ice_get_flash_bank_offset()
475 size = banks->orom_size; in ice_get_flash_bank_offset()
476 active_bank = banks->orom_bank; in ice_get_flash_bank_offset()
479 offset = banks->netlist_ptr; in ice_get_flash_bank_offset()
480 size = banks in ice_get_flash_bank_offset()
465 struct ice_bank_info *banks = &hw->flash.banks; ice_get_flash_bank_offset() local
1328 struct ice_bank_info *banks = &hw->flash.banks; ice_determine_active_flash_banks() local
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_res_part.c64 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_sym_threads()
82 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_asym_threads()
102 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_dc_threads()
125 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb_c4xxx()
176 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb_c4xxx()
/freebsd/sys/arm/allwinner/
H A Daw_gpio.c94 const char *banks; member
105 .banks = "abcdefghi",
117 .banks = "bcdefg",
129 .banks = "abcdefghi",
141 .banks = "abcdefgh",
153 .banks = "abcdefgh",
164 .banks = "lm",
176 .banks = "bcdefgh",
189 .banks = "acdefg",
196 .banks = "l",
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-atlas7.txt7 - gpio-banks : How many gpio banks on this controller
28 gpio-banks = <2>;
H A Dbrcm,kona-gpio.txt8 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
18 number of GPIO banks on the SoC. The interrupts must be ordered by bank,
19 starting with bank 0. There is always a 1:1 mapping between banks and
H A Dmediatek,mt7621-gpio.txt3 The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
4 The registers of all the banks are interwoven inside one single IO range.
H A Dbrcm,brcmstb-gpio.txt5 interrupt is shared for all of the banks handled by the controller.
26 correspond to number of banks suggested by the 'reg' property.
H A Dgpio-stericsson-coh901.txt7 - interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dimg,meta-intc.txt11 - num-banks: Specifies the number of interrupt banks (each of which can
58 // Number of interrupt banks
59 num-banks = <2>;
/freebsd/sys/dev/qat/qat_common/
H A Dadf_vf_isr.c178 TASK_INIT(&priv_data->banks[i].resp_handler, in adf_setup_bh()
181 &priv_data->banks[i]); in adf_setup_bh()
199 &transport->banks[i].resp_handler, in adf_cleanup_bh()
202 &transport->banks[i].resp_handler); in adf_cleanup_bh()
230 struct adf_etr_bank_data *bank = &etr_data->banks[i]; in adf_isr()
H A Dadf_hw_arbiter.c53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb()
73 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_gen2_arb()
187 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
220 csr = accel_dev->transport->banks[0].csr_addr; in adf_disable_arb()
H A Dadf_transport.c189 bank = &trans_data->banks[bank_num]; in adf_poll_bank()
259 bank = &trans_data->banks[bank_num]; in adf_poll_all_banks()
419 bank = &transport_data->banks[bank_num]; in adf_create_ring()
677 etr_data->banks = kzalloc_node(size, in adf_init_etr_data()
703 adf_init_bank(accel_dev, &etr_data->banks[i], i, csr_addr); in adf_init_etr_data()
711 kfree(etr_data->banks); in adf_init_etr_data()
751 cleanup_bank(&etr_data->banks[i]); in adf_cleanup_etr_handles()
771 kfree(etr_data->banks); in adf_cleanup_etr_data()
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dcavium-compact-flash.txt12 - reg: The base address of the CF chip select banks. Depending on
13 the device configuration, there may be one or two banks.
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcavium-mix.txt9 - reg: The base addresses of four separate register banks. The first
16 register banks corresponds to this MIX device.
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-st.txt16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
17 reduces number of overall interrupts numbers required. All these banks belong to
44 with other gpio banks via irqmux.
45 a irqline and gpio banks.
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dqcom,fastrpc.txt41 Each subnode of the Fastrpc represents compute context banks available
43 - All Compute context banks MUST contain the following properties:
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dgpio.txt17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
25 Example of four SOC GPIO banks defined as gpio-controller nodes:
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.txt30 - ranges : Base address and size of the iommu context banks.
49 context banks)
H A Dnvidia,tegra30-smmu.txt5 - reg : Should contain 3 register banks(address and length) for each
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kRegisterBanks.td10 /// Define the M68k register banks used for GlobalISel.
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBanks.td9 // Although RegisterBankSelection is disabled we need to distinct the banks
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-board-base.dtsi22 &memory { /* Default DRAM banks */
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBanks.td10 /// Define the PPC register banks used for GlobalISel.
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dbrcm,brcmstb-reset.txt5 SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
/freebsd/sys/dev/qat/include/common/
H A Dadf_transport_internal.h47 struct adf_etr_bank_data *banks; member

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