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Searched refs:asr (Results 1 – 25 of 35) sorted by relevance

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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Ddivmodsi4.S52 eor ip, r0, r0, asr #31
53 eor lr, r1, r1, asr #31
54 sub r0, ip, r0, asr #31
55 sub r1, lr, r1, asr #31
60 eor r0, r0, r4, asr #31
61 eor r1, r1, r5, asr #31
62 sub r0, r0, r4, asr #31
63 sub r1, r1, r5, asr #31
H A Dmodsi3.S45 eor r2, r0, r0, asr #31
46 eor r3, r1, r1, asr #31
47 sub r0, r2, r0, asr #31
48 sub r1, r3, r1, asr #31
52 eor r0, r0, r4, asr #31
53 sub r0, r0, r4, asr #31
H A Ddivsi3.S61 eor r2, r0, r0, asr #31
62 eor r3, r1, r1, asr #31
63 sub r0, r2, r0, asr #31
64 sub r1, r3, r1, asr #31
74 eor r0, r0, r4, asr #31
75 sub r0, r0, r4, asr #31
H A Dcomparesf2.S119 mvnlo r0, r1, asr #31
136 movhi r0, r1, asr #31
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h29 asr, enumerator
47 case ARM_AM::asr: return "asr"; in getShiftOpcStr()
59 case ARM_AM::asr: return 2; in getShiftOpcEncoding()
H A DARMMCCodeEmitter.cpp251 case ARM_AM::asr: return 2; in getShiftOp()
1595 case ARM_AM::asr: SBits = 0x5; break; in getSORegRegOpValue()
1640 case ARM_AM::asr: SBits = 0x4; break; in getSORegImmOpValue()
1747 case ARM_AM::asr: SBits = 0x4; break; in getT2SORegOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td609 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
615 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
616 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
639 def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
640 def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
H A DARMFastISel.cpp2709 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 }, in ARMEmitIntExt()
2711 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 }, in ARMEmitIntExt()
2713 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 }, in ARMEmitIntExt()
2959 return SelectShift(I, ARM_AM::asr); in fastSelectInstruction()
H A DARMInstrThumb.td1080 "asr", "\t$Rd, $Rm, $imm5",
1091 "asr", "\t$Rdn, $Rm",
1780 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
H A DARMInstructionSelector.cpp1073 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
H A DARMFeatures.td416 // True if codegen should avoid using flag setting movs with shifter operand (i.e. asr, lsl, lsr).
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Ddffma.S230 TMP = asr(CTMPH,#31)
250 CTMP = asr(CTMP,RIGHTSHIFT)
416 ATMP = asr(ATMP,EXPB)
H A Dfastmath2_ldlib_asm.S294 mantd = asr(mantd, #30)
H A Ddfmul.S230 PP_HH = asr(PP_HH,BTMPH)
H A Dfastmath2_dlib_asm.S297 mantexpd = asr(mantexpd, #15)
H A Dfastmath_dlib_asm.S358 lmantc += asr(mantexpd, #15)
H A Ddfsqrt.S297 EXP = asr(EXP,#1) // divide signed exp by 2
/freebsd/sys/crypto/openssl/aarch64/
H A Dvpsm4_ex-armv8.S2738 and w8,w7,w9,asr#31
2743 and w8,w7,w9,asr#31
2748 and w8,w7,w9,asr#31
2753 and w8,w7,w9,asr#31
2758 and w8,w7,w9,asr#31
2763 and w8,w7,w9,asr#31
2768 and w8,w7,w9,asr#31
2780 and w8,w7,w9,asr#31
2790 and w8,w7,w9,asr#31
2800 and w8,w7,w9,asr#31
[all …]
H A Daesv8-armx.S2712 and w11,w19,w22,asr#31
2749 and w11,w19,w22,asr#31
2767 and w11,w19,w22,asr#31
2776 and w11,w19,w22,asr#31
2904 and w11,w19,w22,asr#31
2914 and w11,w19,w22,asr#31
2924 and w11,w19,w22,asr#31
2934 and w11,w19,w22,asr#31
2945 and w11,w19,w22,asr #31
3047 and w11,w19,w22,asr#31
[all …]
H A Dvpsm4-armv8.S2932 and w8,w7,w9,asr#31
2937 and w8,w7,w9,asr#31
2942 and w8,w7,w9,asr#31
2947 and w8,w7,w9,asr#31
2952 and w8,w7,w9,asr#31
2957 and w8,w7,w9,asr#31
2962 and w8,w7,w9,asr#31
3090 and w8,w7,w9,asr#31
3100 and w8,w7,w9,asr#31
3110 and w8,w7,w9,asr#31
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td95 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td61 //Rxx^=asr(Rss,Rt)
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp644 return parsePKHImm(O, ARM_AM::asr, 1, 32); in parsePKHASRImm()
4292 .Case("asr", ARM_AM::asr) in tryParseShiftToken()
4354 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
6168 St = ARM_AM::asr; in parseMemRegOffsetShift()
6202 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) in parseMemRegOffsetShift()
10490 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
10540 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
10572 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
10597 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
10606 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) in processInstruction()
[all …]
/freebsd/sys/crypto/openssl/arm/
H A Decp_nistz256-armv4.S2657 adds r4,r4,r3,asr#31
2659 adcs r5,r5,r3,asr#31
2661 adcs r6,r6,r3,asr#31

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