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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td32 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
41 let AsmString = asmstr;
47 dag outs, dag ins, string asmstr, list<dag> pattern>
48 : MSP430Inst<outs, ins, size, asmstr> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
68 dag outs, dag ins, string asmstr, list<dag> pattern>
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
74 dag outs, dag ins, string asmstr, list<dag> pattern>
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td12 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
19 let AsmString = asmstr;
26 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27 : InstXCore<0, outs, ins, asmstr, pattern> {
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstXCore<2, outs, ins, asmstr, pattern> {
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
25 let AsmString = asmstr;
89 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
103 let AsmString = asmstr;
124 class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
126 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
129 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
131 : I<opcode, OOL, IOL, asmstr, itin> {
141 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_Br
[all...]
H A DPPCInstrMMA.td16 string asmstr> {
20 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
24 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
30 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
34 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
42 string asmstr> {
43 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
49 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
57 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
66 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
[all …]
H A DPPCInstrFutureMMA.td15 string asmstr, list<dag> pattern>
16 : I<opcode, OOL, IOL, asmstr, NoItinerary> {
37 string asmstr, list<dag> pattern>
38 : I<opcode, OOL, IOL, asmstr, NoItinerary> {
56 string asmstr, list<dag> pattern>
57 : I <opcode, OOL, IOL, asmstr, NoItinerary> {
H A DPPCInstrFuture.td15 string asmstr, list<dag> pattern>
16 : I<opcode, OOL, IOL, asmstr, NoItinerary> {
35 string asmbase, string asmstr,
39 !strconcat(asmbase, !strconcat(" ", asmstr)),
43 !strconcat(asmbase, !strconcat(". ", asmstr)),
H A DPPCInstrP10.td111 class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
121 let AsmString = asmstr;
152 class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
154 : I<4, OOL, IOL, asmstr, itin> {
171 string asmbase, string asmstr,
175 !strconcat(asmbase, !strconcat(" ", asmstr)),
179 !strconcat(asmbase, !strconcat(". ", asmstr)),
184 class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
186 : PI<1, opcode, OOL, IOL, asmstr, itin> {
206 class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
[all …]
H A DPPCInstrSPE.td14 class EFXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
16 I<4, OOL, IOL, asmstr, itin> {
29 class EFXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
31 EFXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
35 class EFXForm_2a<bits<11> xo, dag OOL, dag IOL, string asmstr,
37 EFXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
41 class EFXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
43 I<4, OOL, IOL, asmstr, itin> {
55 class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
57 I<4, OOL, IOL, asmstr, itin> {
[all …]
H A DPPCInstrInfo.td736 string asmbase, string asmstr, list<dag> pattern> {
739 !strconcat(asmbase, !strconcat(" ", asmstr)),
743 !strconcat(asmbase, !strconcat(". ", asmstr)),
749 string asmbase, string asmstr, InstrItinClass itin,
753 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
757 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
763 string asmbase, string asmstr, InstrItinClass itin,
768 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
772 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
778 string asmbase, string asmstr, InstrItinClass itin,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td14 class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
20 let AsmString = asmstr;
27 class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : AVRInst<outs, ins, asmstr, pattern> {
35 class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
36 : AVRInst<outs, ins, asmstr, pattern> {
50 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
51 : AVRInst16<outs, ins, asmstr, pattern> {
66 class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
67 list<dag> pattern> : AVRInst16<outs, ins, asmstr, patter
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td12 class XtensaInst<int size, dag outs, dag ins, string asmstr, list<dag> pattern,
22 let AsmString = asmstr;
29 class XtensaInst24<dag outs, dag ins, string asmstr, list<dag> pattern,
31 : XtensaInst<3, outs, ins, asmstr, pattern, itin> {
37 class XtensaInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
39 : XtensaInst<2, outs, ins, asmstr, pattern, itin> {
46 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
47 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
61 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
62 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td9 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
22 let AsmString = asmstr;
36 class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
38 : InstSP<outs, ins, asmstr, pattern, itin> {
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
50 : F2<outs, ins, asmstr, pattern, itin> {
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
60 : F2<outs, ins, asmstr, pattern, itin> {
69 dag outs, dag ins, string asmstr, list<dag> pattern,
71 : InstSP<outs, ins, asmstr, patter
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td96 class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
102 let AsmString = asmstr;
120 class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
121 : InstARC<0, outs, ins, asmstr, pattern> {
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
157 InstARC<4, outs, ins, asmstr, pattern> {
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
167 F32_BR<major, outs, ins, b16, asmstr, pattern> {
175 class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
177 F32_BR<major, outs, ins, b16, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td35 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
44 let AsmString = asmstr;
54 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
56 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
71 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
73 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
81 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
83 MipsInst16_32<outs, ins, asmstr, pattern, itin>
91 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
92 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
[all …]
H A DMips16InstrInfo.td53 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
55 !strconcat(asmstr, "\t$imm11 # 16 bit inst"), [], itin>;
62 class FI816_ins_base<bits<3> _func, string asmstr,
64 FI816<_func, (outs), (ins simm16:$imm8), !strconcat(asmstr, asmstr2),
67 class FI816_ins<bits<3> _func, string asmstr,
69 FI816_ins_base<_func, asmstr, "\t$imm8 # 16 bit inst", itin>;
71 class FI816_SP_ins<bits<3> _func, string asmstr,
73 FI816_ins_base<_func, asmstr, "\t$$sp, $imm8 # 16 bit inst", itin>;
80 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
83 !strconcat(asmstr, asmstr2), [], itin>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrFormats.td23 class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
35 let AsmString = asmstr;
68 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
69 : InstVE<outs, ins, asmstr, pattern> {
94 class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
96 : RM<opVal, outs, ins, asmstr, pattern>;
100 class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
102 : RRM<opVal, outs, ins, asmstr, pattern> {
115 class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
116 : InstVE<outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td17 class WebAssemblyInst<bits<32> inst, string asmstr, bit stack, bit is64>
26 let AsmString = asmstr;
34 string asmstr = "", bits<32> inst = -1, bit is64 = false>
35 : WebAssemblyInst<inst, asmstr, stack, is64> {
44 // based version of this instruction, as well as the corresponding asmstr.
65 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
67 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrFormats.td9 class InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern>
23 let AsmString = asmstr;
86 class InstRI<bits<3> op, dag outs, dag ins, string asmstr,
88 : InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> {
146 class InstRR<bits<3> op, dag outs, dag ins, string asmstr,
148 : InstLanai<outs, ins, asmstr, pattern>, Sched<[WriteALU]> {
196 class InstRM<bit S, dag outs, dag ins, string asmstr, list<dag> pattern>
197 : InstLanai<outs, ins, asmstr, pattern> {
256 class InstRRM<bit S, dag outs, dag ins, string asmstr,
258 : InstLanai<outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td50 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
57 let AsmString = asmstr;
200 class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
201 InstHexagon<outs, ins, asmstr, [], "", itin, type>;
208 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
210 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
212 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
214 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
217 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
219 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
[all …]
H A DHexagonInstrFormatsV65.td23 class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr,
26 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>;
28 class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr,
31 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_GATHER>;
H A DHexagonInstrFormatsV60.td17 class CVI_VA_Resource<dag outs, dag ins, string asmstr,
20 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td13 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
21 let AsmString = asmstr;
187 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
188 : InstSystemZ<2, outs, ins, asmstr, pattern> {
195 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
196 : InstSystemZ<2, outs, ins, asmstr, pattern> {
206 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
207 : InstSystemZ<4, outs, ins, asmstr, pattern> {
220 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
221 : InstSystemZ<6, outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrFormats.td104 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
118 let AsmString = asmstr;
123 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
124 : InstBPF<outs, ins, asmstr, pattern> {
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrFormats.td13 class Op<bits<16> Opcode, dag outs, dag ins, string asmstr, list<dag> pattern = []>
24 let AsmString = asmstr;
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td22 class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
29 let AsmString = asmstr;

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